Proceedings of the 9th International Symposium on Networks-on-Chip最新文献_第2页

Wear-Aware Adaptive Routing for Networks-on-Chips 片上网络的磨损感知自适应路由

Proceedings of the 9th International Symposium on Networks-on-Chip Pub Date : 2015-09-28 DOI: 10.1145/2786572.2786573

A. Vitkovski, V. Soteriou, Paul V. Gratz

引用次数: 1

On-Chip Millimeter Wave Antennas and Transceivers 片上毫米波天线和收发器

Proceedings of the 9th International Symposium on Networks-on-Chip Pub Date : 2015-09-28 DOI: 10.1145/2786572.2789983

Ofer Markish, O. Katz, B. Sheinman, D. Corcos, D. Elad

引用次数: 23

Multi-Layer Test and Diagnosis for Dependable NoCs 可靠NoCs的多层检测与诊断

Proceedings of the 9th International Symposium on Networks-on-Chip Pub Date : 2015-09-28 DOI: 10.1145/2786572.2788708

H. Wunderlich, M. Radetzki

引用次数: 3

A Framework for Combining Concurrent Checking and On-Line Embedded Test for Low-Latency Fault Detection in NoC Routers NoC路由器低延迟故障检测并发检测与在线嵌入式测试相结合的框架

Proceedings of the 9th International Symposium on Networks-on-Chip Pub Date : 2015-09-28 DOI: 10.1145/2786572.2788713

Pietro Saltarelli, Behrad Niazmand, J. Raik, V. Govind, T. Hollstein, G. Jervan, R. Hariharan

{"title":"A Framework for Combining Concurrent Checking and On-Line Embedded Test for Low-Latency Fault Detection in NoC Routers","authors":"Pietro Saltarelli, Behrad Niazmand, J. Raik, V. Govind, T. Hollstein, G. Jervan, R. Hariharan","doi":"10.1145/2786572.2788713","DOIUrl":"https://doi.org/10.1145/2786572.2788713","url":null,"abstract":"The focus of the paper is detection of faults in NoC routers by combining concurrent checkers with embedded on-line test to enable cost-effective trade-offs between area-overhead and test coverage. First, we propose a framework of tools for formally evaluating the quality of the checkers and for optimizing the overhead area with given fault coverage constraints. The stress is in particular on the minimization of the error detection latency, which is a crucial aspect in order to eliminate (or limit) error propagation. Second, the concurrent checkers will be complemented by embedded on-line test packets which are to be applied as a periodic routine during the idle periods in router operation. The framework together with the corresponding methodology has been successfully applied to a realistic case-study of a fault tolerant NoC router design. The case study shows that combining concurrent routers with embedded test allows reducing the area overhead of the checkers from 31--35% down to 1.5--10% without sacrificing the fault coverage.","PeriodicalId":228605,"journal":{"name":"Proceedings of the 9th International Symposium on Networks-on-Chip","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125356496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Modeling and Design of High-Radix On-Chip Crossbar Switches 高基数片上交叉开关的建模与设计

Proceedings of the 9th International Symposium on Networks-on-Chip Pub Date : 2015-09-28 DOI: 10.1145/2786572.2786579

Cagla Cakir, R. Ho, J. Lexau, K. Mai

引用次数: 7

Networking Challenges and Prospective Impact of Broadcast-Oriented Wireless Networks-on-Chip 面向广播的无线片上网络的网络挑战和未来影响

Proceedings of the 9th International Symposium on Networks-on-Chip Pub Date : 2015-09-28 DOI: 10.1145/2786572.2788710

S. Abadal, M. Nemirovsky, E. Alarcón, A. Cabellos-Aparicio

引用次数: 18

Improving DVFS in NoCs with Coherence Prediction 相干预测改善NoCs的DVFS

Proceedings of the 9th International Symposium on Networks-on-Chip Pub Date : 2015-09-28 DOI: 10.1145/2786572.2786595

R. Hesse, Natalie D. Enright Jerger

引用次数: 39

User Cooperation Network Coding Approach for NoC Performance Improvement 面向NoC性能改进的用户协作网络编码方法

Proceedings of the 9th International Symposium on Networks-on-Chip Pub Date : 2015-09-28 DOI: 10.1145/2786572.2786575

Yuankun Xue, P. Bogdan

{"title":"User Cooperation Network Coding Approach for NoC Performance Improvement","authors":"Yuankun Xue, P. Bogdan","doi":"10.1145/2786572.2786575","DOIUrl":"https://doi.org/10.1145/2786572.2786575","url":null,"abstract":"The astonishing rate of sensing modalities and data generation poses a tremendous impact on computing platforms for providing real-time mining and prediction capabilities. We are capable of monitoring thousands of genes and their interactions, but we lack efficient computing platforms for large-scale (exa-scale) data processing. Towards this end, we propose a novel hierarchical Network-on-Chip (NoC) architecture that exploits user-cooperated network coding (NC) concepts for improving system throughput. Our proposed architecture relies on a light-weighted subnet of cooperation unit routers (CUR) for multicast traffic. Coding network interface (CNI) performs encoding/decoding of NC symbols and shares the data flows among cooperation units(CUs). We endow our proposed NC-based NoC architecture with: (i) a corridor routing algorithm (CRA) for maximizing network throughput and (ii) an adaptive flit dropping (AFD) scheme to mitigate congestion, branch-blocking and deadlock at run-time. The experimental results demonstrate that our proposed platform offers up to 127X multicast throughput improvement over multiple-unicast and XY tree-based multicast under synthetic collective traffic scenario. We have evaluated the proposed platform with different realworld benchmarks under network sizes of 4x4 to 32x32. Simulation results show 21%--91% latency improvement and up to 25X runtime reduction over conventional mesh NoC performing genetic-algorithm based protein folding analysis. FPGA implementation results show minimal overhead.","PeriodicalId":228605,"journal":{"name":"Proceedings of the 9th International Symposium on Networks-on-Chip","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121774687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 50

Highway in TDM NoCs TDM NoCs中的高速公路

Proceedings of the 9th International Symposium on Networks-on-Chip Pub Date : 2015-09-28 DOI: 10.1145/2786572.2786577

Shaoteng Liu, Zhonghai Lu, A. Jantsch

{"title":"Highway in TDM NoCs","authors":"Shaoteng Liu, Zhonghai Lu, A. Jantsch","doi":"10.1145/2786572.2786577","DOIUrl":"https://doi.org/10.1145/2786572.2786577","url":null,"abstract":"TDM (Time Division Multiplexing) is a well-known technique to provide QoS guarantees in NoCs. However, unused time slots commonly exist in TDM NoCs. In the paper, we propose a TDM highway technique which can enhance the slot utilization of TDM NoCs. A TDM highway is an express TDM connection composed of special buffer queues, called highway channels (HWCs). It can enhance the throughput and reduce data transfer delay of the connection, while keeping the quality of service (QoS) guarantee on minimum bandwidth and in-order packet delivery. We have developed a dynamic and repetitive highway setup policy which has no dependency on particular TDM NoC techniques and no overhead on traffic flows. As a result, highways can be efficiently established and utilized in various TDM NoCs. According to our experiments, compared to a traditional TDM NoC, adding one HWC with two buffers to every input port of routers in an 8×8 mesh can reduce data delay by up to 80% and increase the maximum throughput by up to 310%. More improvements can be achieved by adding more HWCs per input per router, or more buffers per HWC. We also use a set of MPSoC application benchmarks to evaluate our highway technique. The experiment results suggest that with highway, we can reduce application run time up to 51%.","PeriodicalId":228605,"journal":{"name":"Proceedings of the 9th International Symposium on Networks-on-Chip","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126933396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Dark Silicon: From Computation to Communication 暗硅:从计算到通信

Proceedings of the 9th International Symposium on Networks-on-Chip Pub Date : 2015-09-28 DOI: 10.1145/2786572.2788707

J. Henkel, H. Bokhari, S. Garg, M. U. Khan, Heba Khdr, F. Kriebel, Ümit Y. Ogras, S. Parameswaran, M. Shafique

引用次数: 16