Modeling and Design of High-Radix On-Chip Crossbar Switches

Abstract

The crossbar is a popular topology for on-chip networks that offers non-blocking connectivity and uniform latency. However, as the number of nodes increases, crossbars typically scale poorly in area, power, and latency/throughput. To better understand the design space, we have developed an on-chip crossbar modeling tool based on analytical models calibrated using circuit-level simulation results in 40nm CMOS. We present a design space exploration showing how crossbar area, power, and performance vary across input/output node number, data width, wire parameters, and circuit implementation. Using the modeling results, we identify a design point that demonstrates 2X higher throughput, 1.4X lower power and 1.2X lower area compared to previous published designs.