Proceedings of the 9th International Symposium on Networks-on-Chip最新文献

Highly Fault-tolerant NoC Routing with Application-aware Congestion Management 具有应用感知拥塞管理的高容错性NoC路由

Proceedings of the 9th International Symposium on Networks-on-Chip Pub Date : 2015-09-28 DOI: 10.1145/2786572.2786590

Doowon Lee, Ritesh Parikh, V. Bertacco

{"title":"Highly Fault-tolerant NoC Routing with Application-aware Congestion Management","authors":"Doowon Lee, Ritesh Parikh, V. Bertacco","doi":"10.1145/2786572.2786590","DOIUrl":"https://doi.org/10.1145/2786572.2786590","url":null,"abstract":"Silicon devices are becoming less and less reliable as technology moves to smaller feature sizes. As a result, digital systems are increasingly likely to experience permanent failures during their life-time. To overcome this problem, networks-on-chip (NoCs) should be designed to, not only fulfill performance requirements, but also be robust to many fault occurrences. This paper proposes a fault- and application-aware routing framework called FATE: it leverages the diversity of communication patterns in applications for highly faulty NoCs to reduce congestion during execution. To this end, FATE estimates routing demands in applications to balance traffic load among the available resources. We propose a set of novel route-enabling rules that greatly reduce the search for deadlock-free, maximally-connected routes for any faulty 2D mesh topology, by preventing early on the exploration of routing configuration options that lead eventually to unviable solutions. Our experimental results show a 33% improvement on average saturation throughput for synthetic traffic patterns, and a 59% improvement on average packet latency for SPLASH-2 benchmarks, over state-of-the-art fault-tolerant solutions. The FATE approach is also beneficial in the complete absence of faults: indeed, it outperforms prior fully-adaptive routing techniques by improving the saturation throughput by up to 33%.","PeriodicalId":228605,"journal":{"name":"Proceedings of the 9th International Symposium on Networks-on-Chip","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115766944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

A Low-Overhead, Fully-Distributed, Guaranteed-Delivery Routing Algorithm for Faulty Network-on-Chips 故障片上网络的低开销、全分布式、保证传输路由算法

Proceedings of the 9th International Symposium on Networks-on-Chip Pub Date : 2015-09-28 DOI: 10.1145/2786572.2786591

Mohammad Fattah, A. Airola, Rachata Ausavarungnirun, N. Mirzaei, P. Liljeberg, J. Plosila, S. Mohammadi, T. Pahikkala, O. Mutlu, H. Tenhunen

引用次数: 26

Exploiting Transmission Lines on Heterogeneous Networks-on-Chip to Improve the Adaptivity and Efficiency of Cache Coherence 利用片上异构网络的传输线提高缓存一致性的自适应和效率

Proceedings of the 9th International Symposium on Networks-on-Chip Pub Date : 2015-09-28 DOI: 10.1145/2786572.2786576

Qi Hu, Peng Liu, Michael C. Huang, Xiang-hui Xie

引用次数: 3

Unbiased Regional Congestion Aware Selection Function for NoCs noc的无偏区域拥塞感知选择函数

Proceedings of the 9th International Symposium on Networks-on-Chip Pub Date : 2015-09-28 DOI: 10.1145/2786572.2786574

W. Zong, Michael Opoku Agyeman, Xiaohang Wang, T. Mak

引用次数: 10

An Interconnection Architecture for Seamless Inter and Intra-Chip Communication Using Wireless Links 利用无线链路实现芯片间和芯片内无缝通信的互连体系结构

Proceedings of the 9th International Symposium on Networks-on-Chip Pub Date : 2015-09-28 DOI: 10.1145/2786572.2786581

Md Shahriar Shamim, J. Muralidharan, A. Ganguly

{"title":"An Interconnection Architecture for Seamless Inter and Intra-Chip Communication Using Wireless Links","authors":"Md Shahriar Shamim, J. Muralidharan, A. Ganguly","doi":"10.1145/2786572.2786581","DOIUrl":"https://doi.org/10.1145/2786572.2786581","url":null,"abstract":"With increase in complexity of multicore chips, efficiency of data transfer between cores of a chip is becoming increasingly challenging. Several novel on-chip network architectures are proposed to improve the design flexibility and communication efficiency in multicore chips. On the other hand, computing modules in typical data center nodes or server racks consist of several multicore chips on either a board or in a System-in-Package (SiP) environment. State-of-the-art interchip communication over wireline channels require data signals to travel from internal nets to the peripheral I/O ports and then get routed over the interchip channels to the destination chip. After reaching the destination chip they will be finally routed from the I/O to the internal nets there. This multihop communication increases latency and energy consumption while decreasing data bandwidth in a multichip system. Moreover, intrachip and interchip communication within such a multichip system is often decoupled to facilitate design flexibility. However, a seamless interconnection between on-chip and off-chip data transfer can improve the communication efficiency significantly. In this work we propose the design of a seamless hybrid wired and wireless interconnection network for multichip systems in a package with dimensions spanning up to tens of centimeters with on-chip wireless transceivers. This enables direct chip-to-chip communication between internal cores. We demonstrate with cycle accurate simulations that such a design increases the bandwidth and reduces the energy consumption in comparison to state-of-the-art wireline I/O based multichip communication.","PeriodicalId":228605,"journal":{"name":"Proceedings of the 9th International Symposium on Networks-on-Chip","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125307377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Novel Hybrid Wired-Wireless Network-on-Chip Architectures: Transducer and Communication Fabric Design 新型混合有线-无线片上网络架构:传感器和通信结构设计

Proceedings of the 9th International Symposium on Networks-on-Chip Pub Date : 2015-09-28 DOI: 10.1145/2786572.2786586

Michael Opoku Agyeman, W. Zong, Ji-Xiang Wan, A. Yakovlev, K. Tong, T. Mak

引用次数: 9

Designing High-Performance, Power-Efficient NoCs With Embedded Silicon-in-Silica Nanophotonics 用嵌入硅中硅纳米光子学设计高性能、高能效noc

Proceedings of the 9th International Symposium on Networks-on-Chip Pub Date : 2015-09-28 DOI: 10.1145/2786572.2786588

E. Kakoulli, V. Soteriou, C. Koutsides, K. Kalli

引用次数: 1

Reconfigurable Wireless Network-on-Chip with a Dynamic Medium Access Mechanism 具有动态介质访问机制的可重构无线片上网络

Proceedings of the 9th International Symposium on Networks-on-Chip Pub Date : 2015-09-28 DOI: 10.1145/2786572.2788711

N. Mansoor, A. Ganguly

{"title":"Reconfigurable Wireless Network-on-Chip with a Dynamic Medium Access Mechanism","authors":"N. Mansoor, A. Ganguly","doi":"10.1145/2786572.2788711","DOIUrl":"https://doi.org/10.1145/2786572.2788711","url":null,"abstract":"Wireless interconnects have emerged as an energy-efficient interconnection paradigm for multicore chips with Networks-on-Chips (NoCs). As wireless interconnects have the unique advantage of eliminating the need to layout physical channels they provide an inherent opportunity for dynamic reconfiguration of the NoC architecture. Large temporal and spatial variability in traffic patterns is expected in large multicore chips and especially in future heterogeneous systems-on-chips integrating different kinds of cores such as CPUs, GPUs, ASICs and memory. By establishing on-demand wireless links in response to dynamically varying traffic patterns the data bandwidth and energy efficiency of NoC architectures can be improved compared to static architectures with the same raw bandwidth. We present a dynamic medium access mechanism that establishes wireless links depending on traffic requirements while reducing the overheads. Such an interconnection system incorporating wireless links in a NoC fabric will be better suited to address non-uniformity and temporal variations in traffic patterns which are expected in future large multicore chips.","PeriodicalId":228605,"journal":{"name":"Proceedings of the 9th International Symposium on Networks-on-Chip","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128601833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 27

Achievable Performance Enhancements with mm-Wave Wireless Interconnects in NoC 可实现的性能增强与毫米波无线互连在NoC

Proceedings of the 9th International Symposium on Networks-on-Chip Pub Date : 2015-09-28 DOI: 10.1145/2786572.2786584

G. Harsha, Sujay Deb

引用次数: 8

Runtime Detection of a Bandwidth Denial Attack from a Rogue Network-on-Chip 恶意片上网络带宽拒绝攻击的运行时检测

Proceedings of the 9th International Symposium on Networks-on-Chip Pub Date : 2015-09-28 DOI: 10.1145/2786572.2786580

Rajesh Js, D. Ancajas, Koushik Chakraborty, Sanghamitra Roy

引用次数: 59