Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium最新文献_第2页

A versatile pick and place tool for ultraprecise placement-demonstrated by the application in an advanced MCM-D technology 一种多功能的拾取和放置工具，用于超精密放置-在先进的MCM-D技术中应用

Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium Pub Date : 1997-10-13 DOI: 10.1109/IEMT.1997.626874

P. Guide, O. Bornholdt, G. Neumann

引用次数: 1

Evaluating the manufacturability of GaAs/AlGaAs multiple quantum well avalanche photodiodes using neural networks 利用神经网络评估GaAs/AlGaAs多量子阱雪崩光电二极管的可制造性

Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium Pub Date : 1997-10-13 DOI: 10.1109/IEMT.1997.626885

I. Yun, G. May

{"title":"Evaluating the manufacturability of GaAs/AlGaAs multiple quantum well avalanche photodiodes using neural networks","authors":"I. Yun, G. May","doi":"10.1109/IEMT.1997.626885","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626885","url":null,"abstract":"This paper presents a novel methodology for the parametric yield prediction of GaAs/AlGaAs multiple quantum well (MQW) avalanche photodiodes (APDs). Even in a defect-free manufacturing environment, random variations in the APD fabrication process lead to varying levels of device performance. Accurate performance prediction requires precise characterization of these variations. The approach described herein requires a model of the probability distribution of each of the relevant process variables, as well as a model to account for the correlation between this measured process data and device performance metrics. Neural networks are proposed as a tool for generating these models, which enable the computation of the joint density function required for predicting performance using Jacobian transformation method. The resulting density function can then be numerically integrated to determine parametric yield. In applying this methodology to MQW APDs, using a small number of test devices enables accurate prediction of the expected performance variation of APD gain and noise in larger populations of devices. This approach potentially allows yield estimation prior to high volume manufacturing.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130447021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Eutectic solder bumped flip chip development 共晶焊料碰撞倒装芯片的发展

Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium Pub Date : 1997-10-13 DOI: 10.1109/IEMT.1997.626938

T. Akashi, T. Chikai, T. Hamano, A. Yoshida, S. Honma, H. Aoki, M. Miyata, K. Ezawa, T. Makita, M. Miyaoka

{"title":"Eutectic solder bumped flip chip development","authors":"T. Akashi, T. Chikai, T. Hamano, A. Yoshida, S. Honma, H. Aoki, M. Miyata, K. Ezawa, T. Makita, M. Miyaoka","doi":"10.1109/IEMT.1997.626938","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626938","url":null,"abstract":"Recently, smaller, thinner and higher density packaging technology is demanded. Flip chip interconnection is one of solution to these demands. We have developed solder bumping and wafer sorting processes for bare dice with eutectic solder bumps. The highlights of our solder bumping and wafer sorting process and the reliability test results are shown. The results proved that our bare chips have good reliability, allowing the bumping process to be applied to mass production product. Next we report some experimental results of the wafer sorting process, which is the key process for mass production of bare chips. For peripherally bumped bare chips, we chose a conventional type probing card, the cantilever needle card. We carried out some experiments with four cards which had different needle heads, and decided the best head shape. Using the best card, we investigated the relationship between the overdrive and the amount of bump height deformation. We demonstrated that the deformation can be controlled to smaller than 5 /spl mu/m when operating a 75 /spl mu/m overdrive from all pin contacts. The card can be cleaned better by brushing than by polishing with ceramic plates. To choose probing cards for area bumped bare chips, we did some experiments with three types of probing card: the cantilever type, the bumped type, and the cobra type. Results showed the cobra type is best suited to area bumps.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123197926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

A new test technology for package, module and PCB interconnects 一种新的封装、模块和PCB互连测试技术

Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium Pub Date : 1997-10-13 DOI: 10.1109/IEMT.1997.626893

R. Flake, Sugoog Shon, A. Wong

{"title":"A new test technology for package, module and PCB interconnects","authors":"R. Flake, Sugoog Shon, A. Wong","doi":"10.1109/IEMT.1997.626893","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626893","url":null,"abstract":"This paper discusses an application of a new testing method, Thermal Transmission line Testing (T/sup 3/) for dense packaging interconnects based on measurements of transient thermal signatures along the circuits. The T/sup 3/ methodology has several advantages over current electrical test systems that require numerous built-in module test points and special interconnect probe fixtures designed to reduce their influence on the measurement. The T/sup 3/ system consists of a low power laser, providing a heating pulse to the circuit, together with an IR camera which detects and measures the thermal pulse propagating down the interconnect conductor. The measurement is non-contact, requiring no special interconnect probes. Furthermore, the thermal tests are locally self isolating, meaning that it doesn't matter if the circuit under test is properly terminated or not, since the low power thermal signal decays rapidly. The application of the T/sup 3/ interconnect evaluation technology discussed is the estimation of the contact resistance of TAB Inner Lead Bonds (ILB) and a comparison of these estimates with the subsequent pull test analyses of the leads. A negative trend of ILB contact resistance with bond pull strength is indicated.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114163230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

ViperBGA: a novel design approach to high performance and high density BGA's ViperBGA:一种高性能高密度BGA的新型设计方法

Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium Pub Date : 1997-10-13 DOI: 10.1109/IEMT.1997.626949

P. Wu, K. Chen, J. Tzou

{"title":"ViperBGA: a novel design approach to high performance and high density BGA's","authors":"P. Wu, K. Chen, J. Tzou","doi":"10.1109/IEMT.1997.626949","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626949","url":null,"abstract":"Clock speed requirements will approach 500 MHz and above and thermal requirements of packages will be over 15 watts by the turn of the century as predicted by SIA and electronic industry analysts. The PDA, laptop markets and the cellular markets are increasingly demanding smaller footprint and low cost packaging. ProLinx's ViperBGA with its patented MicroFilled Via technology has been successful in meeting the above market demands. The ViperBGA exhibits a high electrical performance and a high thermal performance at a considerable cost savings compared to current high performance substrates. These enhancements are further optimized by proper use of 3D field solvers as well as extensive use of finite element modeling and the EGA substrate's thermal and electrical parasitics measurements. This paper will discuss a methodology in which modeling combined with ProLinx's BGA designer software is effectively used to optimize the layout of the EGA substrate for high density interconnect routing and optimal placement of electrical and thermal vias for performance enhancements before the manufacturing of the substrates. Measurements are performed after the substrate has been manufactured, and correlated with modeling. Modeling and measurements are done on both the two layer and three layer, cavity down and cavity up substrates.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114519576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Significance of coating stress on substrate bow in large area processing of MCM 涂层应力在MCM大面积加工中的意义

Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium Pub Date : 1997-10-13 DOI: 10.1109/IEMT.1997.626902

Kwanho Yang, J. Im, R. Heistand

{"title":"Significance of coating stress on substrate bow in large area processing of MCM","authors":"Kwanho Yang, J. Im, R. Heistand","doi":"10.1109/IEMT.1997.626902","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626902","url":null,"abstract":"The substrate bow in a large area processing (LAP) was simulated using a finite element analysis (FEA). The structures considered were aluminum (Al) and glass substrates of various thicknesses, and a coating from photosensitive film thickness. It was found that the deflection of a large area substrate, e.g. 400 mm square, could not always be obtained from the linear, small deflection theory even if the curvature might be small and the stress-strain behavior in the linear elastic regime. In this case, the nonlinear, large deflection theory had to be adopted. Also, the gravity effect on the weight of substrate turned out to be very significant and had to be incorporated as well. The simulation incorporating these two factors agreed well with the experimental data, which was generated by spin coating and curing the BCB formulation on Al substrates, 400/spl times/400/spl times/1.27 mm. As a means of flattening out the curvature, subjecting a vacuum underneath the substrate was simulated. Significant reduction of the substrate deflection was observed by applying only a very small vacuum. This result suggested that the use of double-stick tape on the bottom of the substrate, for example, might also be feasible to completely eliminate the bow.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114636836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Energy model for end-of-life computer disposition 报废计算机处置的能量模型

Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium Pub Date : 1997-10-13 DOI: 10.1109/IEMT.1997.626886

T. Aanstoos, V. M. Torres, S. Nichols

引用次数: 10

Assembly and reliability of thermally enhanced high I/O BGA packages 热增强高I/O BGA封装的组装和可靠性

Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium Pub Date : 1997-10-13 DOI: 10.1109/IEMT.1997.626868

T. I. Ejim, D.B. Hollesen, A. Holliday, S. Gahr, R. Coyle

{"title":"Assembly and reliability of thermally enhanced high I/O BGA packages","authors":"T. I. Ejim, D.B. Hollesen, A. Holliday, S. Gahr, R. Coyle","doi":"10.1109/IEMT.1997.626868","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626868","url":null,"abstract":"Surface mount assembly defects for thermally enhanced high I/O, BGAs can range from 0 to 20 ppmj with packages that meet the JEDEC coplanarity specification of 6 mils. Defect levels can be much higher for packages that exceed 6 mils, however. The ability to put surface mount components on both sides of the PWB is desirable in some applications. To facilitate double sided assembly processing, it is recommended that the BGA package weight be kept below 0.038 gms/solder joint to avoid defects during the second side surface mount reflow process where the package is inverted while the solder joints are liquid. Some high I/O packages assembled to PWBs exhibited \"infant mortality\" failures during thermal cycling. These failures were typically at the package/solder ball interface, and were attributed to copper contamination at the electroless nickel/solder interface. Thermal cycling data show that if package metalization quality problems can be resolved, these high I/O packages can meet the severe requirements of telecommunications equipment attachment reliability. Further, data shows that subjecting packages with high temperature solder balls to double side renew processing reduces the attachment reliability of these packages.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"236 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116204792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20

Improvement of microassemblies ultrasonic images using adapted signal processing techniques 应用适应信号处理技术改进微装配超声图像

Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium Pub Date : 1997-10-13 DOI: 10.1109/IEMT.1997.626964

L. Béchou, Y. Ousten, B. Trégon, Y. Danto, M. Salagoity

引用次数: 0

Lot-to-lot analysis of molding compound for PQFP package assembly PQFP封装组件成型材料的批对批分析

Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium Pub Date : 1997-10-13 DOI: 10.1109/IEMT.1997.626894

T. Hongsmatip

{"title":"Lot-to-lot analysis of molding compound for PQFP package assembly","authors":"T. Hongsmatip","doi":"10.1109/IEMT.1997.626894","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626894","url":null,"abstract":"Lot-to-Lot data is needed in order to assure a constant and controlled process. In order to determine the stability of molding compound, we did a full characterization using three lots of material. Elastic modulus, and coefficient of thermal expansion (CTE), glass transition temperature, and filler content were determined using molded test specimens. The same level of understanding is also needed in the area of molding compound rheology. The molding compound viscosity at several shear rates was determined. It was found that lot-to-lot viscosity were similar at high shear rates during the early stage of the reaction. The total heat, rate and %conversion of reaction, and activation energy were calculated. Time and temperature dependence of the molding compound were evaluated by monitoring the rate constant versus time plots. There was no significant difference in CTE and %filler whether the material was molded in 240L PQFP packages or test specimens. However, molded packages were observed to have 10% lower in elastic modulus and 5% lower in Tg than molded test specimens. Finally, effect of moisture ingress in uncured pellets competing of the molding compound was investigated. While information the process capability can be maintained, one critical parameter which can effect the assembly process is moisture. Moisture absorbed by the molding compound showed an influence on a spiral flow test, but it does not appear to significantly change the mechanical properties of the molded packages.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130743627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0