Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)最新文献_第7页

Functional verification of a multiple-issue, out-of-order, superscalar Alpha processor-the DEC Alpha 21264 microprocessor 多问题，无序，超标量Alpha处理器- DEC Alpha 21264微处理器的功能验证

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277208

Scott A. Taylor, M. Quinn, Darren Brown, Nathan Dohm, S. Hildebrandt, J. Huggins, Carl Ramey

引用次数: 72

RF IC design challenges 射频集成电路设计挑战

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277154

B. Razavi

引用次数: 26

General AC constraint transformation for analog ICs 模拟集成电路的通用交流约束变换

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277052

B. G. Arsintescu, E. Charbon, E. Malavasi, U. Choudhury, W. Kao

引用次数: 15

A framework for estimating and minimizing energy dissipation of embedded HW/SW systems 嵌入式硬件/软件系统能耗估算与最小化框架

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1109/DAC.1998.724464

Yanbing Li, J. Henkel

引用次数: 204

A tool for performance estimation of networked embedded end-systems 网络嵌入式终端系统性能评估工具

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277116

A. Kalavade, P. Moghé

{"title":"A tool for performance estimation of networked embedded end-systems","authors":"A. Kalavade, P. Moghé","doi":"10.1145/277044.277116","DOIUrl":"https://doi.org/10.1145/277044.277116","url":null,"abstract":"Networked embedded systems are expected to support adaptive streaming audio/video applications with soft real-time constraints. These systems can be designed in a cost efficient manner only if their architecture exploits the \"leads\" suggested by clever compile time performance estimators. However, performance estimation of networked embedded systems is a non-trivial problem. The computational requirements of such systems show statistical variations that stem from several interacting factors. At the slowest time scale, applications can adapt to network bandwidth by configuring the processing functionality of their task (e.g. compression parameters). Also, there could be significant execution time variations within a task. Thus it is tricky to compute the net processing demand of several such applications on a system architecture, especially if the system schedules these applications using prioritized run-time schedulers. In this paper we describe an analytical tool called AsaP for fast performance estimation of such embedded systems. AsaP builds approximate models of these systems and characterizes the processing load on the system as a stochastic process. The output of AsaP is an exact distribution of the processing delay of each application. This is a powerful result that can be leveraged for efficient design of multimedia networked systems requiring soft real-time guarantees. It is also the first known framework that quantifies the effect of runtime schedulers (FCFS, RM, EDF) on the performance of such systems.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127816173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 57

Asynchronous interface specification, analysis and synthesis 异步接口规范，分析和综合

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277046

M. Kishinevsky, J. Cortadella, A. Kondratyev

引用次数: 21

Design and implementation of the NUMAchine multiprocessor NUMAchine多处理器的设计与实现

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277057

A. Grbic, S. Brown, S. Caranci, R. Grindley, M. Gusat, G. Lemieux, K. Loveless, N. Manjikian, S. Srbljic, M. Stumm, Z. Vranesic, Z. Zilic

引用次数: 30

A practical approach to static signal electromigration analysis 静态信号电迁移分析的一种实用方法

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1109/DAC.1998.724536

Nagaraj Ns, F. Cano, H. Haznedar, D. Young

引用次数: 33

Functional vector generation for HDL models using linear programming and 3-satisfiability 用线性规划和3-可满足性生成HDL模型的功能向量

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277187

F. Fallah, S. Devadas, K. Keutzer

{"title":"Functional vector generation for HDL models using linear programming and 3-satisfiability","authors":"F. Fallah, S. Devadas, K. Keutzer","doi":"10.1145/277044.277187","DOIUrl":"https://doi.org/10.1145/277044.277187","url":null,"abstract":"Our strategy for automatic generation of functional vectors is based on exercising selected paths in the given hardware description language (HDL) model. The HDL model describes interconnections of arithmetic, logic and memory modules. Given a path in the HDL model, the search for input stimuli that exercise the path can be converted into a standard satisfiability checking problem by expanding the arithmetic modules into logic-gates. However, this approach is not very efficient. We present a new HDL-satisfiability checking algorithm that works directly on the HDL model. The primary feature of our algorithm is a seamless integration of linear-programming techniques for feasibility checking of arithmetic equations that govern the behavior of datapath modules, and 3-SAT checking for logic equations that govern the behavior of control modules. This feature is critically important to efficiency, since it avoids module expansion and allows us to work with logic and arithmetic equations whose cardinality tracks the size of the HDL model. We describe the details of the HDL-satisfiability checking algorithm in this paper. Experimental results which show significant speedups over state-of-the-art gate-level satisfiability checking methods are included.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123560340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 90

A DSM design flow: putting floorplanning, technology-mapping, and gate-placement together DSM设计流程:将平面规划、技术制图和闸门布置放在一起

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1109/DAC.1998.724453

Amir H. Salek, J. Lou, Massoud Pedram

引用次数: 27