General AC constraint transformation for analog ICs

Abstract

The problem of designing complex analog circuits is attacked using a hierarchical top-down, constraint-driven design methodology. In this methodology, constraints are propagated automatically from high-level specifications to physical design through a sequence of gradual transformations. Constraint transformation is a critical step in the methodology, since it determines in large part the degree to which specifications are met. In this paper we describe how constraint transformations can be efficiently carried out using hierarchical parameter modeling and constrained optimization techniques. The process supports complex high-level specification handling and accounts for second-order effects, such as interconnect parasitics and mismatches. The suitability of the approach is demonstrated through an 4th order active filter test case.