2020 IEEE 29th Asian Test Symposium (ATS)最新文献

Summing Node Test Method: Simultaneous Multiple AC Characteristics Testing of Multiple Operational Amplifiers 求和节点测试方法:同时测试多个运放的多个交流特性

2020 IEEE 29th Asian Test Symposium (ATS) Pub Date : 2020-11-23 DOI: 10.1109/ATS49688.2020.9301550

Gaku Ogihara, Takayuki Nakatani, Akemi Hatta, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, A. Kuwana, Riho Aoki, Shogo Katayama, Jianglin Wei, Yujie Zhao, Jianlong Wang, K. Hatayama, Haruo Kobayashi

{"title":"Summing Node Test Method: Simultaneous Multiple AC Characteristics Testing of Multiple Operational Amplifiers","authors":"Gaku Ogihara, Takayuki Nakatani, Akemi Hatta, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, A. Kuwana, Riho Aoki, Shogo Katayama, Jianglin Wei, Yujie Zhao, Jianlong Wang, K. Hatayama, Haruo Kobayashi","doi":"10.1109/ATS49688.2020.9301550","DOIUrl":"https://doi.org/10.1109/ATS49688.2020.9301550","url":null,"abstract":"This paper proposes a summing node test method for the operational amplifier and shows the followings: (i) It can be used for parallel testing of multiple AC characteristics (such as open loop gain (AOL), PSRR and CMRR) of one operational amplifier simultaneously with the equivalent accuracy but much faster compared to the NULL method. Also it can measure them even for multiple operational amplifiers at the same time. (ii) It can measure THD, SNR and THD+N of the operational amplifier with the comparable accuracy to the audio analyzer usage case, by applying proper analog filters. In other words, it can measure them with remarkable accuracy at very low cost. These have been verified with simulations and experiments. The proposed summing node test method uses an inverting operational amplifier under test and its negative input is amplified by an auxiliary non-inverting operational amplifier. The input and power supply voltages for the operational amplifier under test are modulated by AC signals with different frequencies. The auxiliary amplifier output is digitized after analog filtering and FFT is performed to the digitized data. This proposed method can reduce operational amplifier test time with good accuracy but without expensive instruments at mass production shipping, to meet the requirements for IoT and automotive as well as audio applications.","PeriodicalId":220508,"journal":{"name":"2020 IEEE 29th Asian Test Symposium (ATS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115316420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Unexpected Error Explosion in NAND Flash Memory: Observations and Prediction Scheme NAND快闪记忆体中的意外错误爆炸:观察与预测方案

2020 IEEE 29th Asian Test Symposium (ATS) Pub Date : 2020-11-23 DOI: 10.1109/ATS49688.2020.9301575

Yuqian Pan, Haichun Zhang, Mingyang Gong, Zhenglin Liu

{"title":"Unexpected Error Explosion in NAND Flash Memory: Observations and Prediction Scheme","authors":"Yuqian Pan, Haichun Zhang, Mingyang Gong, Zhenglin Liu","doi":"10.1109/ATS49688.2020.9301575","DOIUrl":"https://doi.org/10.1109/ATS49688.2020.9301575","url":null,"abstract":"Wear-out has been a critical reliability problem in NAND flash memory. As executing repeated program and erase operations on the NAND flash chips, the number of errors increases and ultimately exceeds the ECC capability. In previous work, error characteristics of flash wear-out are observed by endurance tests on a single type of NAND flash memory. We wonder if the experimental results cover the entire error characteristics of NAND flash memory. In this paper, we tested more than 20 types of NAND flash chips with different vendors and structures and presented an overlook of test results. Through the test results, we found an unexpected error-explosion phenomenon that errors of flash blocks first increase over several cycles and then reach a high value without warning. We analyzed the features of the error-explosion and explored its influence on operation time. And we propose an error-explosion prediction scheme to find the blocks that will occur an error-explosion in the next 1000 P/E cycles. The block identifying operation is realized by the machine-learning model. The performance of six machine-learning methods is compared. The results demonstrate that the Decision Trees and Bagged Classification Trees have the best accuracy.","PeriodicalId":220508,"journal":{"name":"2020 IEEE 29th Asian Test Symposium (ATS)","volume":"167 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114493337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Survey: Hardware Trojan Detection for Netlist 调查:硬件木马检测的网表

2020 IEEE 29th Asian Test Symposium (ATS) Pub Date : 2020-11-23 DOI: 10.1109/ATS49688.2020.9301614

Yipei Yang, Jing Ye, Yuan Cao, Jiliang Zhang, Xiaowei Li, Huawei Li, Yu Hu

引用次数: 11

ATS 2020 Preface

2020 IEEE 29th Asian Test Symposium (ATS) Pub Date : 2020-11-23 DOI: 10.1109/ats49688.2020.9301505

引用次数: 0

Power Supply Noise-Aware Scan Test Pattern Reshaping for At-Speed Delay Fault Testing of Monolithic 3D ICs * 单片三维集成电路高速延迟故障检测的电源噪声感知扫描测试模式重构*

2020 IEEE 29th Asian Test Symposium (ATS) Pub Date : 2020-11-23 DOI: 10.1109/ATS49688.2020.9301568

Shao-Chun Hung, Yi-Chen Lu, S. Lim, K. Chakrabarty

引用次数: 4

ATS Steering Committee 2020-2022 ATS指导委员会2020-2022

2020 IEEE 29th Asian Test Symposium (ATS) Pub Date : 2020-11-23 DOI: 10.1109/ats49688.2020.9301602

引用次数: 0

Exploring the Mysteries of System-Level Test 探索系统级测试的奥秘

2020 IEEE 29th Asian Test Symposium (ATS) Pub Date : 2020-11-23 DOI: 10.1109/ATS49688.2020.9301557

I. Polian, J. Anders, Steffen Becker, P. Bernardi, K. Chakrabarty, N. Elhamawy, M. Sauer, A. Singh, M. Reorda, S. Wagner

引用次数: 23

Validating GCSE in the scheduling of high-level synthesis 验证GCSE在高级合成调度中的应用

2020 IEEE 29th Asian Test Symposium (ATS) Pub Date : 2020-11-23 DOI: 10.1109/ATS49688.2020.9301546

Jian Hu, Yongyang Hu, Long Yu, Haitao Yang, Yun Kang, Jie Cheng

引用次数: 0

BTI Aging Monitoring based on SRAM Start-up Behavior 基于SRAM启动行为的BTI老化监测

2020 IEEE 29th Asian Test Symposium (ATS) Pub Date : 2020-11-23 DOI: 10.1109/ATS49688.2020.9301603

Shengyu Duan, Peng Wang, G. Sai

{"title":"BTI Aging Monitoring based on SRAM Start-up Behavior","authors":"Shengyu Duan, Peng Wang, G. Sai","doi":"10.1109/ATS49688.2020.9301603","DOIUrl":"https://doi.org/10.1109/ATS49688.2020.9301603","url":null,"abstract":"Bias Temperature Instability (BTI) is one of the dominant CMOS aging mechanisms. It causes time-dependent variation, threatening circuit lifetime reliability. BTI-induced circuit errors are not detectable at the fabrication stage. On-line monitoring schemes are therefore necessary to capture the degradations during the operational time. Traditional aging monitoring techniques exhibit high implementation complexity and low stability. In this paper, we propose a BTI monitoring approach by simply tracking the start-up behavior of SRAM cells. SRAM is a widely used on-chip device in many applications. We study the impact of BTI for SRAM start-up values and age some cells in a manipulated manner. The BTI degradation is evaluated based on the number of SRAM cells starting with a certain value. This technique can be used to estimate the degradation for on-chip logic circuits without introducing additional circuitry, and thus has very low implementation complexity. We use an SRAM array with 1024 cells to estimate the degradations for multiple logic circuits, and show the average mean absolute percentage error as 8.48%. In addition, this technique is robust considering process, voltage and temperature variations.","PeriodicalId":220508,"journal":{"name":"2020 IEEE 29th Asian Test Symposium (ATS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131475944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An ADC Test Technique With Dual-Path/Multi-Functional Fine Pattern Generator Realizing High Accuracy Measurement for CMOS Image Sensor 一种实现CMOS图像传感器高精度测量的双路/多功能精细图形发生器ADC测试技术

2020 IEEE 29th Asian Test Symposium (ATS) Pub Date : 2020-11-23 DOI: 10.1109/ATS49688.2020.9301531

F. Morishita, M. Otsuka, Wataru Saito

引用次数: 4