2020 IEEE 29th Asian Test Symposium (ATS)最新文献_第2页

Student Committee 学生委员会

2020 IEEE 29th Asian Test Symposium (ATS) Pub Date : 2020-11-23 DOI: 10.1109/ats49688.2020.9301542

引用次数: 0

Artificial Neuron Hardware IP Verification 人工神经元硬件IP验证

2020 IEEE 29th Asian Test Symposium (ATS) Pub Date : 2020-11-23 DOI: 10.1109/ATS49688.2020.9301543

Teo Sje Yin, Soon Ee Ong

引用次数: 1

ATS 2020 Index

2020 IEEE 29th Asian Test Symposium (ATS) Pub Date : 2020-11-23 DOI: 10.1109/ats49688.2020.9301567

引用次数: 0

A Testability Enhancement Method for the Memristor Ratioed Logic Circuits 忆阻率逻辑电路的可测试性增强方法

2020 IEEE 29th Asian Test Symposium (ATS) Pub Date : 2020-11-23 DOI: 10.1109/ATS49688.2020.9301537

Li Qu, Xiaole Cui, Xiaohui Cui

{"title":"A Testability Enhancement Method for the Memristor Ratioed Logic Circuits","authors":"Li Qu, Xiaole Cui, Xiaohui Cui","doi":"10.1109/ATS49688.2020.9301537","DOIUrl":"https://doi.org/10.1109/ATS49688.2020.9301537","url":null,"abstract":"The Resistive Random Access Memory (RRAM) is a two-terminal variable resistance device, and the memristor ratioed logic (MRL) is a hybrid RRAM-CMOS style of logic circuit. The MRL AND and OR gates are implemented by the RRAM devices, and the MRL NOT gate is implemented by the CMOS inverter. However, the MRL circuits are prone to test escape. This work proposes a method to improve the testability of MRL circuits by replacing the CMOS inverters with the FinFET inverters. The test escape problem is solved by adjusting the switching threshold voltages of the FinFET inverters, and it is implemented by selecting the FinFET inverters in different operation modes. In Addition, some equivalent relationships in the fault set of the improved MRL gates are discovered. These fault equivalences of MRL gates result in a fault collapse ratio of about 50%. The test patterns for the production test of the improved MRL circuits can be generated by the traditional ATPG method. The test results of some typical MRL circuits obtained from the commercial ATPG tool show that the proposed method is able to achieve 100% fault coverage and at least 55% fault collapse ratio.","PeriodicalId":220508,"journal":{"name":"2020 IEEE 29th Asian Test Symposium (ATS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133952293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Analysis and Design of Multi-Tone Signal Generation Algorithms for Reducing Crest Factor 降低波峰因子的多音信号生成算法分析与设计

2020 IEEE 29th Asian Test Symposium (ATS) Pub Date : 2020-11-23 DOI: 10.1109/ATS49688.2020.9301549

Y. Shibasaki, Koji Asami, Riho Aoki, Akemi Hatta, A. Kuwana, Haruo Kobayashi

引用次数: 1

Scan Chain Diagnosis-Driven Test Response Compactor 扫描链诊断驱动的测试响应压缩器

2020 IEEE 29th Asian Test Symposium (ATS) Pub Date : 2020-11-23 DOI: 10.1109/ATS49688.2020.9301584

Jakub Janicki, Grzegorz Mrugalski, Artur Stelmach, Szczepan Urban

引用次数: 0

LBIST-PUF: An LBIST Scheme Towards Efficient Challenge-Response Pairs Collection and Machine-Learning Attack Tolerance Improvement LBIST- puf:一种有效的挑战-响应对收集和提高机器学习容忍度的LBIST方案

2020 IEEE 29th Asian Test Symposium (ATS) Pub Date : 2020-11-23 DOI: 10.1109/ATS49688.2020.9301590

Michihiro Shintani, Tomoki Mino, M. Inoue

{"title":"LBIST-PUF: An LBIST Scheme Towards Efficient Challenge-Response Pairs Collection and Machine-Learning Attack Tolerance Improvement","authors":"Michihiro Shintani, Tomoki Mino, M. Inoue","doi":"10.1109/ATS49688.2020.9301590","DOIUrl":"https://doi.org/10.1109/ATS49688.2020.9301590","url":null,"abstract":"Device identification using challenge-response pairs (CRPs), in which the response is obtained from a physically unclonable function (PUF), is a promising countermeasure for the counterfeit of integrated circuits (ICs). To achieve secure device identification, a large number of CRPs are collected by the manufacturers, thereby increasing the measurement costs. This paper proposes a novel scheme, which employs a logic built-in self-test (LBIST) circuit, to efficiently collect the CRPs during production tests. As a result, no additional measurement is required for the CRP collection. In addition, the proposed technique can counter machine-learning (ML) attacks because of the complicated relationship between challenge and response through the LBIST circuit. Through the proof-of-concept implementation, in which a field-programmable gate array (FPGA) is used, we demonstrate the PUF performance can be evaluated by a test pattern generated by the LBIST circuit. Furthermore, the vulnerability due to ML attacks using a support vector machine (SVM) and random forest (RF) is lowered by more than two times compared to the naive usage of PUF.","PeriodicalId":220508,"journal":{"name":"2020 IEEE 29th Asian Test Symposium (ATS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114907440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Pre-silicon Noise to Timing Test Methodology 预硅噪声定时测试方法

2020 IEEE 29th Asian Test Symposium (ATS) Pub Date : 2020-11-23 DOI: 10.1109/ATS49688.2020.9301514

F. Tan, Jia Yun Chuah

引用次数: 0

Theoretical Analysis on Noise Performance of Modulated Wideband Converters for Analog Testing 模拟测试用调制宽带变换器噪声性能的理论分析

2020 IEEE 29th Asian Test Symposium (ATS) Pub Date : 2020-11-23 DOI: 10.1109/ATS49688.2020.9301596

Zolboo Byambadorj, Koji Asami, Takahiro J. Yamaguchi, Akio Higo, M. Fujita, T. Iizuka

引用次数: 0

On-chip EOL Prognostics Using Data-Fusion of Embedded Instruments for Dependable MP-SoCs 使用可靠的mp - soc嵌入式仪器数据融合的片上EOL预测

2020 IEEE 29th Asian Test Symposium (ATS) Pub Date : 2020-11-23 DOI: 10.1109/ATS49688.2020.9301509

Ghazanfar Ali, Leila Bagheriye, H. Manhaeve, H. Kerkhoff

引用次数: 0