一种实现CMOS图像传感器高精度测量的双路/多功能精细图形发生器ADC测试技术

F. Morishita, M. Otsuka, Wataru Saito
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引用次数: 4

摘要

本文提出了一种用于CMOS图像传感器(CIS)芯片内模数转换器(adc)高精度测量的新电路和技术。由于用于CIS输入的光信号源难以管理和控制,因此对此类adc的评估一直是一个很大的挑战。测试电路提供双路,一条用于正常工作,另一条用于将外部电输入信号直接应用于ADC。该测试路径还具有多功能精细模式生成器的能力,可以为每个列定义任何输入,以评估CIS特定的特性。该测试电路和技术可以直接从CIS芯片测量ADC的特性。测量结果显示,INL为15 LSB,串扰为20 LSB,加速柱干扰为5 LSB。这些测量结果与设计值一致。通过这种简单的电路和技术,我们确定了14位的测量精度。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An ADC Test Technique With Dual-Path/Multi-Functional Fine Pattern Generator Realizing High Accuracy Measurement for CMOS Image Sensor
This paper proposes a novel circuit and technique for high accuracy measurement of analog-to-digital converters (ADCs) within a CMOS image sensor (CIS) chip. The evaluation of such ADCs has been a big challenge because optical signal source for CIS input is difficult to manage and control. The test circuit provides a dual path, one for normal operation and the other for applying external electrical input signal directly to ADC. This test path also has an ability of multi-functional fine pattern generator that can define any input for each column to evaluate CIS specific characteristics. This test circuit and technique enables the measurement of ADC characteristics directly from CIS chip. Measured result shows INL of 15 LSB, crosstalk of 20 LSB and accelerated column interference of 5 LSB. These measured results agreed with the designed values. With this straightforward circuit and technique, we confirmed the measurement accuracy of 14-bit.
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