Validating GCSE in the scheduling of high-level synthesis

Jian Hu, Yongyang Hu, Long Yu, Haitao Yang, Yun Kang, Jie Cheng
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Abstract

High-level synthesis (HLS) compiles a algorithmic description (C or C++) into a digital hardware implementation (VHDL or Verilog) through a sequence of transformations. However, the complex compiling process may introduce an error in the produced register-transfer level (RTL) implementation. Global common subexpression elimination (GCSE) as a commonly used code motion technique in the scheduling of HLS is an error-prone and complex process that need to be validated. In this paper, we propose an equivalence checking method to validate GCSE with non-common variables used in the rest code in the scheduling of HLS by enhancing the path equivalence criteria. The source and target programs are modeled using Finite State Machine with Datapath (FSMD) that is essentially a Control and Data Flow Graph (CDFG). The experimental results show that our method can indeed validate the GCSE with non-common variables used in the rest code in HLS which has not been solved in the existing papers.
验证GCSE在高级合成调度中的应用
高级综合(HLS)通过一系列转换将算法描述(C或c++)编译成数字硬件实现(VHDL或Verilog)。然而,复杂的编译过程可能会在生成的寄存器传输级(RTL)实现中引入错误。全局公共子表达式消除(GCSE)作为HLS调度中常用的一种代码运动技术,是一个容易出错且复杂的过程,需要进一步验证。本文提出了一种等价检验方法,通过增强路径等价准则来验证HLS调度中剩余代码中使用的非公共变量的GCSE。源程序和目标程序使用具有数据路径的有限状态机(FSMD)建模,FSMD本质上是一个控制和数据流图(CDFG)。实验结果表明,我们的方法确实可以验证HLS中剩余代码中使用的非公共变量的GCSE,这是现有论文没有解决的问题。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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