发布求助
文献互助 智能选刊 最新文献

Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits最新文献

筛选
英文 中文
Characterization of hot-carrier degradation in non-isolated MOSFETs using a new gate-current measurement technique 用一种新的门电流测量技术表征非隔离mosfet中的热载流子退化
Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 1995-11-27 DOI: 10.1109/IPFA.1995.487603
S. Leang, D. Chan, W. Chim
{"title":"Characterization of hot-carrier degradation in non-isolated MOSFETs using a new gate-current measurement technique","authors":"S. Leang, D. Chan, W. Chim","doi":"10.1109/IPFA.1995.487603","DOIUrl":"https://doi.org/10.1109/IPFA.1995.487603","url":null,"abstract":"With the continual miniaturization of MOS devices, hot-carrier degradation has become a major reliability issue. Several techniques have been developed to characterize the hot-carrier degradation in MOSFETs. Of these, the gate-current measurement and charge-pumping techniques have been shown to be particularly attractive. However, only the gate-current measurement technique can be used on non-isolated, practical devices. A new gate-current measurement technique is developed, which requires a much shorter time to obtain the I/sub g/-V/sub g/ characteristic curves of MOSFETs as compared to the conventional floating gate technique.","PeriodicalId":216880,"journal":{"name":"Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122175118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Intelligent defect localization methodology through the use of photoemission spectral analysis 利用光电光谱分析的智能缺陷定位方法
Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 1995-11-27 DOI: 10.1109/IPFA.1995.487594
Jeong-Seon Seo, Sang-sik Lee, C. Choe, K. Hong, S. Daniel, C. Yoon
{"title":"Intelligent defect localization methodology through the use of photoemission spectral analysis","authors":"Jeong-Seon Seo, Sang-sik Lee, C. Choe, K. Hong, S. Daniel, C. Yoon","doi":"10.1109/IPFA.1995.487594","DOIUrl":"https://doi.org/10.1109/IPFA.1995.487594","url":null,"abstract":"Point defects in CMOS circuits may generate single or multiple emission spots, not necessarily coincident with the physical defect. In this study we show how photoemission spectrum analysis (PSA) is used to discount secondary emissions. Spectrum-based defect layer judgements enable intelligent, targeted etch-back decisions. The feasibility of performing backside PSA analysis is also discussed.","PeriodicalId":216880,"journal":{"name":"Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114992482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Silicate contamination on ceramic IC packages and its effect on lid adhesion properties 陶瓷IC封装上的硅酸盐污染及其对封装盖附着性能的影响
Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 1995-11-27 DOI: 10.1109/IPFA.1995.487627
B. Chin, K. Lim, Y. C. Chong
{"title":"Silicate contamination on ceramic IC packages and its effect on lid adhesion properties","authors":"B. Chin, K. Lim, Y. C. Chong","doi":"10.1109/IPFA.1995.487627","DOIUrl":"https://doi.org/10.1109/IPFA.1995.487627","url":null,"abstract":"This paper presents a case history of a packaging failure that was caused by contamination introduced in one of the processes on the assembly line. Results of the failure analysis via the use of the X-Ray Photoelectron Spectroscopy (XPS) for contamination at various stages of the Ceramic Pin Grid Array (CPGA) packaging assembly process, and an analysis of the contact angles obtained from the ceramic substrate surface to indicate wettability are presented.","PeriodicalId":216880,"journal":{"name":"Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131113097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effect of oxide field on hot carrier induced degradation in CMOS gate oxide 氧化场对CMOS栅极氧化物热载子诱导降解的影响
Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 1995-11-27 DOI: 10.1109/IPFA.1995.487602
S. P. Zhao, S. Taylor
{"title":"Effect of oxide field on hot carrier induced degradation in CMOS gate oxide","authors":"S. P. Zhao, S. Taylor","doi":"10.1109/IPFA.1995.487602","DOIUrl":"https://doi.org/10.1109/IPFA.1995.487602","url":null,"abstract":"In this study, substrate hot electron injection (SHE) experiments have been carried out on n-MOSFETs. The effects of the oxide field on the hot electron induced degradation has been studied systematically. The oxide field dependence of the trapping over the field range from 0.5 to 6 MV/cm for different injection levels has been investigated.","PeriodicalId":216880,"journal":{"name":"Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121828009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Reliability testing of GaAs MMICs GaAs mmic的可靠性测试
Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 1995-11-27 DOI: 10.1109/IPFA.1995.487616
W. Anderson, J. Roussos, K. Christianson
{"title":"Reliability testing of GaAs MMICs","authors":"W. Anderson, J. Roussos, K. Christianson","doi":"10.1109/IPFA.1995.487616","DOIUrl":"https://doi.org/10.1109/IPFA.1995.487616","url":null,"abstract":"GaAs MMICs were reliability life tested under accelerated high temperature conditions while operating under normal bias conditions under RF drive. These circuits (EG6010 power amplifiers) were standard evaluation circuit (SEC) deliverables on the US Department of Defense ARPA MIMIC Program. The median life, t50, was found to be 1/spl times/10/sup 7/ hours at a channel temperature of 140/spl deg/C, with an activation energy of 1.4 eV. Failure analysis revealed that circuit degradation and burnout were the result of failure of the field effect transistors (FETs). Hot spots were found to occur at the FET fingers that were covered by air bridges and could not be plated with gold for better heat dissipation. Excess leakage currents at the hot spots were found to be responsible for circuit degradation and burnout.","PeriodicalId":216880,"journal":{"name":"Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115276050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
VMESS: VLSI mechanical stress simulator VMESS: VLSI机械应力模拟器
Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 1995-11-27 DOI: 10.1109/IPFA.1995.487623
A. Bhattacharyya, D.N. Singh, R. Metha, I. Goswami
{"title":"VMESS: VLSI mechanical stress simulator","authors":"A. Bhattacharyya, D.N. Singh, R. Metha, I. Goswami","doi":"10.1109/IPFA.1995.487623","DOIUrl":"https://doi.org/10.1109/IPFA.1995.487623","url":null,"abstract":"In a systematic study the mechanical stress build up due to the thermal cycling on a silicon wafer with the deposition of overlay films has been modelled taking into account the plasticity introduced in such films when the stress exceeds a critical value. The measurement of mechanical stress in a production CMOS process has been carried out. A VLSI MEchanical Stress Simulator (VMESS) is developed using this integrated model for calculating thermal component of the mechanical stress in a silicon wafer. Using this simulator, it has been shown that the mechanical stress could be engineered at macro level by adjusting the deposition parameters of the films.","PeriodicalId":216880,"journal":{"name":"Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125406040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Plasma damage study using fully processed MOS transistors 使用全加工MOS晶体管的等离子体损伤研究
Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 1995-11-27 DOI: 10.1109/IPFA.1995.487612
V. Prabhakar, T. Brożek, X. Li, Y. Chan, C. Viswanathan
{"title":"Plasma damage study using fully processed MOS transistors","authors":"V. Prabhakar, T. Brożek, X. Li, Y. Chan, C. Viswanathan","doi":"10.1109/IPFA.1995.487612","DOIUrl":"https://doi.org/10.1109/IPFA.1995.487612","url":null,"abstract":"MOS transistors with different antenna ratios were used to study plasma etching damage in this work. Electrical techniques that can only be used in MOS transistors, such as transconductance noise measurements, charge pumping measurements, and gate induced drain leakage measurements (GIDL) were employed to study plasma damage at the gate edges. Experiments were also performed to determine hot carrier reliability, and the results indicate the importance of plasma induced damage for actual device operation.","PeriodicalId":216880,"journal":{"name":"Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134394844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Temperature cycle-induced die metal shearing in surface mount devices after infra red/vapour phase reflow 红外/气相回流后表面贴装器件中温度循环引起的模具金属剪切
Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 1995-11-27 DOI: 10.1109/IPFA.1995.487628
S. Kumar, Goh Jing Sua, D.L.T. Wai
{"title":"Temperature cycle-induced die metal shearing in surface mount devices after infra red/vapour phase reflow","authors":"S. Kumar, Goh Jing Sua, D.L.T. Wai","doi":"10.1109/IPFA.1995.487628","DOIUrl":"https://doi.org/10.1109/IPFA.1995.487628","url":null,"abstract":"Moisture-induced \"popcorn\" effect in surface mount devices during infra red or vapour phase reflow manifests itself as visible cracks originating from the edges of the die or the leadframe mount pad. More robust packages often give rise to only microcracks after reflow which subsequently require further thermal stresses to induce device or package failure. This paper analyses the secondary effect of die metal shearing in SOJ packages subjected to temperature cycling after an infra red reflow. This phenomenon has significant bearing on the current practice of preconditioning packages using infra red or vapour phase reflow before subjecting them to reliability tests like temperature cycling. A model is developed to explain the relationship between package microcracks after reflow and subsequent metal shearing when subjected to temperature cycling. The metal shear lines are characterised using failure analysis techniques to validate the model. Various methods of improving the SOJ package resistance to microcracking during reflow are discussed.","PeriodicalId":216880,"journal":{"name":"Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133334993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IGBT power semiconductor reliability analysis for traction application 牵引应用IGBT功率半导体可靠性分析
Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 1995-11-27 DOI: 10.1109/IPFA.1995.487618
P. Jacob, M. Held, P. Scacco
{"title":"IGBT power semiconductor reliability analysis for traction application","authors":"P. Jacob, M. Held, P. Scacco","doi":"10.1109/IPFA.1995.487618","DOIUrl":"https://doi.org/10.1109/IPFA.1995.487618","url":null,"abstract":"IGBT (Insulated Gate Bipolar Transistor) power semiconductor modules become of importance for traction applications. However, the reliability of these power modules is still a concern, compared to those of press-packed GTOs. Although first IGBT-press-pack solutions have been presented to the market, IGBT-presspacking remains difficult and expensive. Besides this, customers prefer module technology solutions, because of their economical advantage and easiness of device mounting. Reliability tests have been developed and modules have been analyzed to judge critical reliability points and to show ways for improvement.","PeriodicalId":216880,"journal":{"name":"Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122295715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Design and implementation of a fully testable CMOS D-latch 一个完全可测试的CMOS d锁存器的设计和实现
Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 1995-11-27 DOI: 10.1109/IPFA.1995.487622
C. Aissi, J. Olaniyan
{"title":"Design and implementation of a fully testable CMOS D-latch","authors":"C. Aissi, J. Olaniyan","doi":"10.1109/IPFA.1995.487622","DOIUrl":"https://doi.org/10.1109/IPFA.1995.487622","url":null,"abstract":"A fully testable CMOS D-latch (FTD) is proposed. Earlier work had considered D-latches testable by only a limited set of faults. In this paper, a comprehensive test set is developed. This test set is then applied to the FTD. The cost of implementation, analysis and simulation of the FTD are all carried out. Application of the FTD-latch to build a polarity-hold shift register is shown.","PeriodicalId":216880,"journal":{"name":"Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124674267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信
小红书