Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits最新文献_第4页

CMOS ESD protection structures-characteristics and performance comparison CMOS ESD保护结构-特性与性能比较

Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 1995-11-27 DOI: 10.1109/IPFA.1995.487605

R. Fried, Y. Blecher, S. Friedman

引用次数: 1

A new interlayer dielectric (ILD) cracking mechanism in ceramic packaged multilayered CMOS devices 一种新的陶瓷封装多层CMOS器件层间介电(ILD)开裂机制

Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 1995-11-27 DOI: 10.1109/IPFA.1995.487610

Yeoh Eng Hong, Chong Aik Kean, R. Tay

引用次数: 0

A study of the microcracks on the alumina of the thin-film head 薄膜头部氧化铝微裂纹的研究

Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 1995-11-27 DOI: 10.1109/IPFA.1995.487619

A. Chekanov, T. S. Low, S. Alli

引用次数: 0

Guard ring diodes for suppression of substrate noise and improved reliability in mixed-mode CMOS circuits 保护环二极管用于抑制衬底噪声和提高混合模式CMOS电路的可靠性

Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 1995-11-27 DOI: 10.1109/IPFA.1995.487613

L. Forbes, W.T. Lim, K. T. Yan

引用次数: 7

A study of integrated circuit I-V characteristics using a fault localization system [FLS] 基于故障定位系统的集成电路I-V特性研究[FLS]

Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 1995-11-27 DOI: 10.1109/IPFA.1995.487599

L.T.S. Quah, W. K. Wong, J. Phang, D.S.H. Chan, P.Y.S. Ho

引用次数: 0

The effect of some geometric and packaging process parameters on die metallization failure 一些几何参数和封装工艺参数对模具金属化失效的影响

Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 1995-11-27 DOI: 10.1109/IPFA.1995.487590

A. Tay, S. H. Ong, Y. K. Lim

引用次数: 5

A study of the influence of inter-metal dielectrics on electromigration performance 金属间介质对电迁移性能影响的研究

Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 1995-11-27 DOI: 10.1109/IPFA.1995.487615

S. Foley, A. Ryan, D. Martin, A. Mathewson

引用次数: 10

Thickness dependence of low-level leakages in thin oxides 薄氧化物中低泄漏的厚度依赖性

Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 1995-11-27 DOI: 10.1109/IPFA.1995.487608

S. Gladstone, R. S. Scott, E. Runnion, T. W. Hughes, D. Dumin, J.C. Mitros, L. Lie

{"title":"Thickness dependence of low-level leakages in thin oxides","authors":"S. Gladstone, R. S. Scott, E. Runnion, T. W. Hughes, D. Dumin, J.C. Mitros, L. Lie","doi":"10.1109/IPFA.1995.487608","DOIUrl":"https://doi.org/10.1109/IPFA.1995.487608","url":null,"abstract":"The wearout of 4 nm to 13 nm thick oxides fabricated on n-type and p-type substrates was measured. The interface trap densities, flatband voltage shifts, bulk trap densities and low-level leakage currents were measured before and after high-voltage stressing. In oxides that had been stressed at the equivalent electric fields for constant times, the measured flatband voltage shifts, interface trap densities, and bulk trap densities dropped as the oxide thicknesses dropped and were negligible for oxides thinner than 6 nm, while the low-level pre-tunneling leakage currents increased. Both an AC and a DC component to the stress-induced low-level leakages were measured. The DC component to this leakage current increased as the oxide thicknesses decreased. A model based on uniform trap generation throughout the oxide during the high-voltage stresses and tunnel charge/discharge of the traps within approximately 3 nm of either interface after the stresses were removed, has been used to explain and accurately fit all of the thickness dependences of the trap generation and leakage current measurements. The thickness dependent leakage currents will limit oxides to thicknesses greater than about 10 nm for non-volatile memory applications.","PeriodicalId":216880,"journal":{"name":"Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122529792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Focused ion beam sample preparation for high spatial resolution X-ray microanalysis 高空间分辨率x射线微分析的聚焦离子束样品制备

Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 1995-11-27 DOI: 10.1109/IPFA.1995.487593

K. Pey, A. Leslie

引用次数: 0

Finite element analysis of hygrothermally induced stresses in plastic IC packages 塑料IC封装湿热应力的有限元分析

Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 1995-11-27 DOI: 10.1109/IPFA.1995.487592

S. Yi, Jing Sua Goh, Ji Cheng Yang

{"title":"Finite element analysis of hygrothermally induced stresses in plastic IC packages","authors":"S. Yi, Jing Sua Goh, Ji Cheng Yang","doi":"10.1109/IPFA.1995.487592","DOIUrl":"https://doi.org/10.1109/IPFA.1995.487592","url":null,"abstract":"In the present study, the moisture and temperature distributions and residual stresses inside plastic encapsulated IC packages are evaluated in order to asses product reliability. Numerical procedures based on finite element analyses are presented to calculate the hygro-thermally induced deformations and stresses in plastic IC packages during the surface mounting process preceded by the moisture soaking test. For example residual stresses in thin LOC (Lead-On-Chip) TSOP packages during the reflow soldering process preceded by the 168 hours 85/spl deg/C/85% RH moisture soaking test have been studied. Numerical results show that when TSOP packages undergo the reflow soldering process substantially high tensile /spl sigma//sub 2/ stresses arose in the silicon chip while high compressive stresses were in the encapsulant below the chip. Such high compressive and tensile stress development in the silicon chip and encapsulant below the chip is responsible for the delamination and popcorn crack. The results also show that the magnitudes of residual stresses in IC packages may depend not only on the magnitude of loading but also on the loading history due to the hygro-thermo-viscoelastic behavior of plastic mold compound materials.","PeriodicalId":216880,"journal":{"name":"Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129353906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2