Design and implementation of a fully testable CMOS D-latch

Abstract

A fully testable CMOS D-latch (FTD) is proposed. Earlier work had considered D-latches testable by only a limited set of faults. In this paper, a comprehensive test set is developed. This test set is then applied to the FTD. The cost of implementation, analysis and simulation of the FTD are all carried out. Application of the FTD-latch to build a polarity-hold shift register is shown.