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Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits最新文献

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Double through-transmission ultrasonic inspection of plastic IC packages 塑料IC封装的双透透射超声检测
Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 1995-11-27 DOI: 10.1109/IPFA.1995.487591
Ji Cheng Yang, Jing Sua Goh
{"title":"Double through-transmission ultrasonic inspection of plastic IC packages","authors":"Ji Cheng Yang, Jing Sua Goh","doi":"10.1109/IPFA.1995.487591","DOIUrl":"https://doi.org/10.1109/IPFA.1995.487591","url":null,"abstract":"A double through transmission ultrasonic technique for IC package inspection is presented. The technique makes use of a smooth plate under the IC package to reflect the ultrasound that has passed through the package. The reflected ultrasound goes through the package again and is received for signal and image processing to detect internal defects in the IC package. The technique overcomes the difficulties of the traditional pulse-echo SAM methods. It also offers advantages over the through transmission setup in the market. The technique was successfully applied to reveal the internal defects such as delamination and package crack in thin packages.","PeriodicalId":216880,"journal":{"name":"Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125683986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A method for reducing complex MOS structures in switch level simulators 一种简化开关电平模拟器中复杂MOS结构的方法
Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 1995-11-27 DOI: 10.1109/IPFA.1995.487600
C. Aissi, D. Gobovic, J. Olaniyan
{"title":"A method for reducing complex MOS structures in switch level simulators","authors":"C. Aissi, D. Gobovic, J. Olaniyan","doi":"10.1109/IPFA.1995.487600","DOIUrl":"https://doi.org/10.1109/IPFA.1995.487600","url":null,"abstract":"A new method is proposed for simplifying complex MOS structures in switch level simulators. It is shown that the well known technique of circuit analysis can be applied to the shape factor \"S\" of different MOS transistors. This allows an equivalent transistor strength to be easily computed. The obtained results are applicable to both NMOS and CMOS structures. Examples are given to illustrate the use of the method.","PeriodicalId":216880,"journal":{"name":"Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"53 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134512008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The related effects of increased PN junction area on ESD protection capability 增大PN结面积对ESD防护能力的相关影响
Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 1995-11-27 DOI: 10.1109/IPFA.1995.487607
Liu Po-Ching, B. Lee, E. Lian, G. Hock, W. Haibo
{"title":"The related effects of increased PN junction area on ESD protection capability","authors":"Liu Po-Ching, B. Lee, E. Lian, G. Hock, W. Haibo","doi":"10.1109/IPFA.1995.487607","DOIUrl":"https://doi.org/10.1109/IPFA.1995.487607","url":null,"abstract":"ESD protection devices comprising polysilicon resistor, Vcc and Vss connected diodes with different sizes of PN junction area were fabricated on CMOS test chip and underwent ESD stress. The result of testing shows that larger PN junction area will subject the polysilicon resistor to bear more energy from ESD stress and end up with more failures. The relationship between stressing energy and junction area is hereby derived. Different failure modes for positive and negative ESD pulses are also identified. By comparing our own design with those of commercial designs, a safe length of contacting parameter at Al-polysilicon contact capable of handling the discharging current is identified to be more than 90 /spl mu/m.","PeriodicalId":216880,"journal":{"name":"Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115565693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Challenges for IC failure analysis-present and future 集成电路失效分析的挑战-现在和未来
Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 1995-11-27 DOI: 10.1109/IPFA.1995.487587
R. E. Anderson, J. Soden, C. Henderson, E. I. Cole
{"title":"Challenges for IC failure analysis-present and future","authors":"R. E. Anderson, J. Soden, C. Henderson, E. I. Cole","doi":"10.1109/IPFA.1995.487587","DOIUrl":"https://doi.org/10.1109/IPFA.1995.487587","url":null,"abstract":"Failure analysis is a critical element in integrated circuit manufacturing. This paper explores the challenges for IC failure analysis in the environment of present and future silicon IC technology trends, using the 1994 National Technology Roadmap for Semiconductors as a technology guide. Advanced techniques that meet the challenges of state-of-the-art IC technology are described and their applications are discussed. New approaches shall be required for failure analysis to keep pace with future advancements in IC technology.","PeriodicalId":216880,"journal":{"name":"Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121822374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Oxidation of copper leadframe 铜引线架的氧化
Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 1995-11-27 DOI: 10.1109/IPFA.1995.487626
G. Ang, L. C. Goh, K. W. Heng, Susanta Lahiri
{"title":"Oxidation of copper leadframe","authors":"G. Ang, L. C. Goh, K. W. Heng, Susanta Lahiri","doi":"10.1109/IPFA.1995.487626","DOIUrl":"https://doi.org/10.1109/IPFA.1995.487626","url":null,"abstract":"Delamination of the oxide film from copper alloy leadframes is considered a serious reliability problem for microelectronics packages. In an effort to identify the factors which may lead to the formation of brittle and/or poorly adhering oxides, kinetics of oxidation of leadframes in air was investigated by measuring the oxide thickness as a function of time at temperatures ranging from 200 to 300/spl deg/C. The oxidation was found to occur fairly rapidly in this temperature range. Analysis of the data indicates a logarithmic growth law in the 100-1400 nm thickness range, and an activation energy which is much smaller than that reported for the oxidation of unalloyed copper by a diffusion mechanism. The results of this investigation is presented here indicating the important role of defects in the oxidation of leadframe.","PeriodicalId":216880,"journal":{"name":"Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129336940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Hot-carrier induced degradation in the subthreshold characteristics of LDD PMOSFETs 热载流子诱导的LDD pmosfet亚阈值特性退化
Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 1995-11-27 DOI: 10.1109/IPFA.1995.487601
C. Lou, W. Chim, D.S.H. Chan, Y. Pan
{"title":"Hot-carrier induced degradation in the subthreshold characteristics of LDD PMOSFETs","authors":"C. Lou, W. Chim, D.S.H. Chan, Y. Pan","doi":"10.1109/IPFA.1995.487601","DOIUrl":"https://doi.org/10.1109/IPFA.1995.487601","url":null,"abstract":"Hot-carrier injection is shown to degrade the subthreshold operation of LDD PMOSFETs. Hot-carrier injection is observed to increasingly degrade the subthreshold leakage and subthreshold slope as the LDD PMOSFETs are scaled to smaller dimensions. A physical model, based on the channel shortening effect of degraded PMOSFETs, is used to model the degradation characteristics observed. Degradation in the subthreshold characteristics of PMOSFETs is expected to limit the life of PMOSFETs as its channel length is reduced to half-a-micrometer.","PeriodicalId":216880,"journal":{"name":"Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129768105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A new oxide breakdown degradation phenomenon in CMOS transistors CMOS晶体管中一种新的氧化物击穿降解现象
Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 1995-11-27 DOI: 10.1109/IPFA.1995.487614
T. Yeoh, Shze-Jer Hu
{"title":"A new oxide breakdown degradation phenomenon in CMOS transistors","authors":"T. Yeoh, Shze-Jer Hu","doi":"10.1109/IPFA.1995.487614","DOIUrl":"https://doi.org/10.1109/IPFA.1995.487614","url":null,"abstract":"The degradation of CMOS inverter circuit performance due to transistor gate oxide breakdown is studied in this paper. This is based on the different gate oxide breakdown sites i.e., gate to drain/source or gate to substrate/well breakdown of p- and n-channel transistors. Gate to drain breakdown of either por n- channel transistor significantly degrades inverter performance.","PeriodicalId":216880,"journal":{"name":"Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"55 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114131172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Surface analysis and application in magnetic hard disk media 磁性硬盘介质的表面分析及应用
Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 1995-11-27 DOI: 10.1109/IPFA.1995.487621
R. Gopalakrishnan
{"title":"Surface analysis and application in magnetic hard disk media","authors":"R. Gopalakrishnan","doi":"10.1109/IPFA.1995.487621","DOIUrl":"https://doi.org/10.1109/IPFA.1995.487621","url":null,"abstract":"Surface Techniques (XPS, AES and SIMS) are gaining popularity in recent years as an indispensable analytical tool in providing synergistic approach to solve technological problems. To illustrate the capabilities and limitations of these techniques, a wide number of practical examples in the area of magnetic disk media are presented and discussed. These examples include: measurement of loop thickness, composition of magnetic thin films, nature and quality of interface, impurity and contamination studies at micro/macroscopic regions, failure analysis etc.","PeriodicalId":216880,"journal":{"name":"Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128734116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Poly-3 bitline crack [DRAMs] Poly-3位线裂纹[dram]
Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 1995-11-27 DOI: 10.1109/IPFA.1995.487624
W. Tan, Lee Keat Peng, Giam Siang Tian
{"title":"Poly-3 bitline crack [DRAMs]","authors":"W. Tan, Lee Keat Peng, Giam Siang Tian","doi":"10.1109/IPFA.1995.487624","DOIUrl":"https://doi.org/10.1109/IPFA.1995.487624","url":null,"abstract":"The increasing trend in cold temperature failures has reached a high level and the predominant fail label is LRAS:RMW. Electrical Failure Analysis (EFA) of Pre (T1) & Post (T2) burn-in ADSEL and XMC failures revealed a consistent pattern of bits that failed along a column. Through the understanding of the device layout, a poly-3 bitline twist crack fault model is proposed and confirmed subsequently through Physical Failure Analysis (PFA). As an extension to this finding, electrical characterization of LRAS:RMW C/T failures also showed the same failmode, though of lesser severity. An effective guardband test is developed at room temp to screen out this category of failure. This test achieved minimal impact to overall testtime and overkill. Process & design actions were initiated at Waferfab & Design to resolve the poly-3 crack issue, with preliminary evaluation data showing promising results. A short discussion of the lessons learnt is included, in particular the fanning out of waferfab & design changes to other device type using the same bitline twist architecture.","PeriodicalId":216880,"journal":{"name":"Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115750410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A new spectroscopic photon emission microscope system for semiconductor device analysis 用于半导体器件分析的新型光谱光子发射显微镜系统
Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 1995-11-27 DOI: 10.1109/IPFA.1995.487596
Y.Y. Liu, J. Tao, D.S.H. Chan, J. Phang, W. Chim
{"title":"A new spectroscopic photon emission microscope system for semiconductor device analysis","authors":"Y.Y. Liu, J. Tao, D.S.H. Chan, J. Phang, W. Chim","doi":"10.1109/IPFA.1995.487596","DOIUrl":"https://doi.org/10.1109/IPFA.1995.487596","url":null,"abstract":"This paper describes the design and performance of a new spectroscopic photon emission microscope system (SPEMS) with panchromatic imaging and continuous wavelength spectroscopic capabilities. Very low levels of light emissions from biased devices can be detected and high resolution spectral characteristics can be analysed because of the highly efficient light collection and transmission optics. Results shown include that of MOS transistors biased in saturation, forward and reverse biased pn junctions and oxide leakage. The potential use of the 'defect finger-printing' technique, whereby a unique spectral signature is assigned to each failure mechanism, is also discussed.","PeriodicalId":216880,"journal":{"name":"Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"11 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121856160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
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