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2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)最新文献

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Toward fast low power adaptive spike sorting VLSI chip design for wireless BCI implants 面向无线脑接口植入的快速低功耗自适应尖峰分选VLSI芯片设计
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282139
Zaghloul Saad Zaghloul, M. Bayoumi
{"title":"Toward fast low power adaptive spike sorting VLSI chip design for wireless BCI implants","authors":"Zaghloul Saad Zaghloul, M. Bayoumi","doi":"10.1109/MWSCAS.2015.7282139","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282139","url":null,"abstract":"Recently, controlling the surrounding world by just the power of our thoughts has become a reality using Brain Computer/Machine Interface (BCI/BMI). Enabling handicap people to control artificial limbs is one of the most important goals of BCI. There are challenges in providing the usability of BCI implants because most of the BCI sensors are non-practical or increases the infection hazard to the patients. Some research proposed wireless implants that do not require chronic wound in the skull. However, in such cases, the communications consume much power via a slow and complex arithmetic unit, high power and bandwidth that exceeds the allowed limits [1]. This study proposes and implements a neural based real-time spike sorting technique for wireless BCI that is faster and simpler than the existing designs, which was achieved by simplifying the computational units, restricting fixed point architecture and involving an adaptive immune system structure based behavior; which makes the design also power and area efficient. The system was implemented, and simulated using Modalism and Cadence.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121894061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Design of compact packaged switched reconfigurable multi-band BPF using LTCC technology 基于LTCC技术的紧凑封装开关可重构多频段BPF设计
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282144
A. M. Elelimy, A. El-Tager, A. Sobih
{"title":"Design of compact packaged switched reconfigurable multi-band BPF using LTCC technology","authors":"A. M. Elelimy, A. El-Tager, A. Sobih","doi":"10.1109/MWSCAS.2015.7282144","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282144","url":null,"abstract":"This paper presents a novel reconfigurable tri-band BPF embedded in a low temperature co-fired ceramics (LTCC) package designed with two-state frequency responses, where tri-band and dual-band bandpass characteristics can be conveniently switched by turning chip scale pin diodes on and off. The filter can operate as a tri-band BPF with center frequencies 2.1 GHz, 3.5 GHz and 5.8 GHz for UMTS and WiMAX applications. On the other hand, it can operate only at 3.5 GHz and 5.8 GHz for WiMAX rejecting 2.1 GHz UMTS signals. The design proposes simple resonance stripline structures integrated with chip pin diodes. Bias circuits are designed and optimized with precisely selected practical lumped components. The proposed reconfigurable filter is simulated and optimized. The filter provides significant size reduction and superior enhancement in insertion losses.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124943043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of an MTJ-based nonvolatile lookup table circuit using an energy-efficient single-ended logic-in-memory structure 基于mtj的非易失性查找表电路设计，采用高能效的单端内存逻辑结构
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282195
D. Suzuki, T. Hanyu
{"title":"Design of an MTJ-based nonvolatile lookup table circuit using an energy-efficient single-ended logic-in-memory structure","authors":"D. Suzuki, T. Hanyu","doi":"10.1109/MWSCAS.2015.7282195","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282195","url":null,"abstract":"A 6-input nonvolatile lookup table (LUT) circuit is proposed using an energy-efficient single-ended logic-in-memory (LIM) structure in conjunction with a magnetic tunnel junction (MTJ) device. While the use of a conventional single-ended LIM structure makes the multi-input LUT circuit compact, a long delay due to the small difference in the MTJ resistance and a large amount of dynamic power consumption due to a DC current path are unavoidable. To overcome the problem, a PMOS feedback transistor which makes it possible to accelerate the logic operation is utilized in the proposed LUT circuit. The use of the PMOS feedback transistor also makes it possible to reduce dynamic power consumption by automatically cutting off the DC current just after logic value `0' is read. In fact, the power-delay product of the proposed 6-input LUT circuit is reduced by 66% in comparison with that of the conventional single-ended one under a 90-nm CMOS technology.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125673059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Novel single-input single-output two-box polar behavioral model for envelope tracking power amplifiers 包络跟踪功率放大器的新型单输入单输出双箱极性行为模型
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282202
Saif Najmeddine, O. Hammi
{"title":"Novel single-input single-output two-box polar behavioral model for envelope tracking power amplifiers","authors":"Saif Najmeddine, O. Hammi","doi":"10.1109/MWSCAS.2015.7282202","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282202","url":null,"abstract":"In this paper, a two-box polar behavioral model is proposed for envelope tracking power amplifiers. The proposed model is built using the parallel combination of the generalized memory polynomial function and a memoryless polynomial function applied to the input signal's magnitude and its phase, respectively. The proposed model is experimentally validated using a Gallium Nitride based envelope tracking power amplifier driven by multi-carrier test signals. The model performance was assessed against that of the conventional generalized memory polynomial model. The results demonstrate that the proposed model consistently outperforms the conventional model in terms of accuracy and complexity. The proposed model converges to an NMSE that is 1dB better than that of the conventional model while requiring significantly lower number of coefficients.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130056058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A precise 360°-range phase detector for fdNIRS application using a pair of XNORs 一种精确的360°范围相位检测器，用于fdNIRS应用，使用一对XNORs
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282161
Siavash S. Yazdi, A. Cerussi, Michael M. Green
{"title":"A precise 360°-range phase detector for fdNIRS application using a pair of XNORs","authors":"Siavash S. Yazdi, A. Cerussi, Michael M. Green","doi":"10.1109/MWSCAS.2015.7282161","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282161","url":null,"abstract":"A novel circuit for precise phase detection between two signals with the same frequency is presented. It is shown how the non-idealities in conventional phase detectors give rise to nonlinearities in the average voltage vs. phase characteristic. The proposed circuit makes use of a pair of XNOR-type phase detectors, to which signal and quadrature reference clocks are applied. A decision circuit then selects which of the two XNORs is used for the output, which guarantees that the circuit will be well within its linear region.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124361620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Electrical circuit modeling of a PEM fuel cell including compressor effect 考虑压缩效应的PEM燃料电池电路建模
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282053
Mahmoud Nabag, A. Fardoun, H. Hejase, A. Al-Marzouqi
{"title":"Electrical circuit modeling of a PEM fuel cell including compressor effect","authors":"Mahmoud Nabag, A. Fardoun, H. Hejase, A. Al-Marzouqi","doi":"10.1109/MWSCAS.2015.7282053","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282053","url":null,"abstract":"This study aims to investigate the development of an Electrical Circuit Model (ECM) that represents the behavior of a PEM fuel cell system. The ECM parameters are identified based on sets of impedance data obtained by using a characterization process known as Electrochemical Impedance Spectroscopy (EIS). The measured impedance is fitted to an ECM using a nonlinear least-square fitting method. The proposed ECM is able to represent the effect of the compressor. The proposed model is validated using a commercial fuel cell power module. In general, such model representation is useful for analyzing the effects of the operating conditions on the fuel cell performance, efficiency and durability.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122636591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Architecture comparison for concurrent multi-band linear power amplifiers 并行多频带线性功率放大器的结构比较
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282166
Zhen Zhang, Yifei Li, N. Neihart
{"title":"Architecture comparison for concurrent multi-band linear power amplifiers","authors":"Zhen Zhang, Yifei Li, N. Neihart","doi":"10.1109/MWSCAS.2015.7282166","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282166","url":null,"abstract":"In this paper, a comparison between the concurrent multi-band and parallel single-band power amplifier architectures is analyzed. A generalized framework in which these two architectures can be compared in terms of cost, drain efficiency, output power, and linearity is developed. Results show that in general, a concurrent multi-band power amplifier will have worse performance than a parallel single-band amplifier for class-A operation, to the point that it is not a viable substitution. Class-B and class-C operation, however, remain viable alternatives for area savings without a large drop in efficiency and output power.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"976 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123083213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Buffer sizing of concentrated photovoltaic batteries: An economic analysis 聚光光伏电池缓冲尺寸:经济分析
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282057
Y. Moumouni, R. J. Baker
{"title":"Buffer sizing of concentrated photovoltaic batteries: An economic analysis","authors":"Y. Moumouni, R. J. Baker","doi":"10.1109/MWSCAS.2015.7282057","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282057","url":null,"abstract":"Energy storage systems are one of the major components in today's grid-tied photovoltaic technology. The most widespread ESSs are the batteries mounted on electric vehicles. Second-life batteries, regardless of the technology, are less expensive than new battery packs. The proper sizing of concentrated photovoltaic buffers and the true economic feasibility need to be investigated thoroughly before any large-scale photovoltaic grid integration. This paper investigates the economic performance of grid-tied concentrated photovoltaics and buffers. Simulation results show that not only is the combined unit capable of connection to the grid during the day at a constant 20 kW, but also was able to shift the less valuable off-peak electric supply to the on-peak supply, where the cost of electricity was higher. This paper addresses (1) techniques behind battery-sizing scenarios, (2) battery-parameter calculations involved in concentrated photovoltaic output smoothing and/or electrical load shifting, and (3) used electric vehicle battery cost estimation. Estimates of the cost effectiveness could be positive if the energy storage system battery pack prices drop to $375/kWh or lower.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115755133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A two-dimensional chaotic logic gate for improved computer security 一种提高计算机安全性的二维混沌逻辑门
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282078
James W. Bohl, Lok K. Yan, G. Rose
{"title":"A two-dimensional chaotic logic gate for improved computer security","authors":"James W. Bohl, Lok K. Yan, G. Rose","doi":"10.1109/MWSCAS.2015.7282078","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282078","url":null,"abstract":"In recent years the concept of chaos-based computing has emerged as a way to harness the rich state space of chaotic systems for robust computation. Potential advantages of such chaotic computational elements include improved security in the form of logic obfuscation and power analysis mitigation. For example, the chaotic nature of computation leads to a chaotic power profile that is difficult to use for side-channel attacks. In this paper, we explore the construction of chaotic logic gates based on Chua's circuit. We propose a two-dimensional chaotic logic gate that utilizes the two state variables of Chua's circuit to implement all possible two-input logic functions. Further, the likelihood of any logic function is shown to approach 1/16 as the evolution time of the gate is increased. Equally likely functions are beneficial from a security perspective in that the power profile and potentially the logic itself can be obfuscated from potential attackers. It is difficult to determine the effective logic function without knowledge of past states.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"416 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115925578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A process tolerant semi-self impedance calibration method for LPDDR4 memory controller LPDDR4存储器控制器的过程容错半自阻抗校准方法
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2015-10-01 DOI: 10.1109/MWSCAS.2015.7282070
Ho Joon Lee, Yong-Bin Kim
{"title":"A process tolerant semi-self impedance calibration method for LPDDR4 memory controller","authors":"Ho Joon Lee, Yong-Bin Kim","doi":"10.1109/MWSCAS.2015.7282070","DOIUrl":"https://doi.org/10.1109/MWSCAS.2015.7282070","url":null,"abstract":"This paper presents a novel process variation compensation technique for semi-self impedance calibration of the transmission line driver implemented with the Low Voltage Swing Terminated Logic (LVSTL). The impedance calibration in the pull-up and pull-down networks of the driver circuits are analyzed and designed based on the JEDEC LPDDR4(Low Power Double Data Rate) standard. Based on the impedance mismatch analysis, a new semi-self impedance calibration circuit for LPDDR4 is proposed to compensate the driver impedance mismatch caused by the process variation using process monitoring circuit. The proposed circuit is designed and implemented with 180nm CMOS technology using 1.8V supply voltage. With the proposed semi-self calibration circuit, ± VOH level change due to process variations is reduced by 81% in pull-up and 74% in pull-down networks without power overhead because it is foreground calibration scheme.","PeriodicalId":216613,"journal":{"name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116879860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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