Feng Qian, Wenli Du, W. Zhong, Yang Tang, Jingyi Lu
{"title":"Artificial intelligence-assisted design of new chemical materials: a perspective","authors":"Feng Qian, Wenli Du, W. Zhong, Yang Tang, Jingyi Lu","doi":"10.1007/s11432-023-4096-9","DOIUrl":"https://doi.org/10.1007/s11432-023-4096-9","url":null,"abstract":"","PeriodicalId":21618,"journal":{"name":"Science China Information Sciences","volume":null,"pages":null},"PeriodicalIF":7.3,"publicationDate":"2024-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141823501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Review of chiplet-based design: system architecture and interconnection","authors":"Yafei Liu, Xiangyu Li, Shouyi Yin","doi":"10.1007/s11432-023-3926-8","DOIUrl":"https://doi.org/10.1007/s11432-023-3926-8","url":null,"abstract":"<p>Chiplet-based design, which breaks a system into multiple smaller dice (or “chiplets”) and reassembles them into a new system chip through advanced packaging, has received extensive attention in the post Moore’s law era due to its advantages in terms of cost, performance, and agility. However, significant challenges arise in this implementation approach, including the mapping of functional components onto chiplets, co-optimization of package and architecture, handling the increased latency of communication across functions in different dies, the uncertainty problems of fragment communication subsystems, such as maintaining deadlock-free when independently designed chiplets are combined. Despite various design approaches that attempt to address these challenges, surveying these approaches one-after-another is not the most helpful way to offer a comparative viewpoint. Accordingly, in this paper, we present a more comprehensive and systematic strategy to survey the various approaches. First, we divide them into chiplet-based system architecture design and interconnection design, and further classify them based on different architectures and building blocks of interconnection. Then, we analyze and cross-compare each classification separately, and in addition, we present a topical discussion on the evolution of memory architectures, design automation, and other relevant topics in chiplet-based designs. Finally, some discussions on important topics are presented, emphasizing future needs and challenges in this rapidly evolving field.</p>","PeriodicalId":21618,"journal":{"name":"Science China Information Sciences","volume":null,"pages":null},"PeriodicalIF":8.8,"publicationDate":"2024-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141786024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 56 Gb/s DAC-DSP-based transmitter with adaptive retiming clock optimization using inverse-PR-based PD achieving 8-UI converge time in 28-nm CMOS","authors":"Shubin Liu, Chenxi Han, Xiaoteng Zhao, Yuhao Zhang, Shixin Li, Hongzhi Liang, Lihong Yang, Zhangming Zhu","doi":"10.1007/s11432-024-4072-9","DOIUrl":"https://doi.org/10.1007/s11432-024-4072-9","url":null,"abstract":"<p>This work presents an adaptive clock optimization scheme for TX to alleviate the timing constraints for the retimer. Using the PR and inverse-PR-based phase detector, the optimal clock phase is selected for retiming with only 8 UI convergence time. By adopting the proposed technique, we realize a 1–56 Gb/s DAC-DSP-based TX in 28-nm CMOS. Measurement results show that the rising edge of retiming clock is located in the center of data when the phase adjustment completed. The total TX consumes 164 mWat 56-Gb/s PAM4 signaling with 97.8% RLM in 0.25 mm<sup>2</sup> area. Therefore, the proposed retiming clock optimization scheme is a promising scheme for high-speed TX.</p>","PeriodicalId":21618,"journal":{"name":"Science China Information Sciences","volume":null,"pages":null},"PeriodicalIF":8.8,"publicationDate":"2024-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141784753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Zhangming Zhu, Jun Chang, Hongzhi Liang, Ruixue Ding, Shubin Liu
{"title":"A 10-GS/s 8-bit 2× time interleaved hybrid ADC with λ/4 reference T-Line sharing technique","authors":"Zhangming Zhu, Jun Chang, Hongzhi Liang, Ruixue Ding, Shubin Liu","doi":"10.1007/s11432-024-4082-9","DOIUrl":"https://doi.org/10.1007/s11432-024-4082-9","url":null,"abstract":"<p>A 10-GS/s 8-bit 2× time interleaved hybrid ADC with λ/4 reference T-Line sharing technique has been demonstrated. Meanwhile, an on-chip 5th HILO with a center frequency of 20 GHz is embedded to generate the low-jitter propagation signal for T-Lines. The proposed sharing reference T-Line technique and serpentine routing enable a significant improvement on silicon-area efficiency. The ADC achieves a measured 3-dB effective bandwidth close to 6.7 GHz and an ENOB exceeding 5.5. The hybrid ADC chip fabricated in 0.9-V 28-nm CMOS achieves a 10-GS/s sampling frequency with a 31.22-mW power consumption. At Nyquist input, the SNDR is 38.11 dB, while at over-Nyquist 7.89 GHz input, the SNDR is 34.2 dB.</p>","PeriodicalId":21618,"journal":{"name":"Science China Information Sciences","volume":null,"pages":null},"PeriodicalIF":8.8,"publicationDate":"2024-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141740297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A CSP-based retraining framework for motor imagery based brain-computer interfaces","authors":"Xue Jiang, Lubin Meng, Xinru Chen, Dongrui Wu","doi":"10.1007/s11432-024-4081-x","DOIUrl":"https://doi.org/10.1007/s11432-024-4081-x","url":null,"abstract":"<p>CSP is one of the most widely used signal processing approaches in EEG-based MI classification; however, the CSP optimization objective is not completely consistent with the final classification objective, and hence it does not necessarily lead to the best classification performance. This study has proposed a retraining framework, which retrains a neural network with the same forward computational process and initial parameters as the CSP-based traditional model, and further optimizes it on the labeled training data using gradient descent. Experiments on four MI datasets demonstrated that retraining improved traditional models’ classification performance and outperformed several popular deep neural network models, especially when the amount of labeled training data was very small. Our work demonstrates the advantage of integrating knowledge from traditional models and from the training data in EEG-based BCIs.</p>","PeriodicalId":21618,"journal":{"name":"Science China Information Sciences","volume":null,"pages":null},"PeriodicalIF":8.8,"publicationDate":"2024-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141740298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Keqin Liu, Bingjie Dang, Zhiyu Yang, Teng Zhang, Zhen Yang, Jinxuan Bai, Zelun Pan, Ru Huang, Yuchao Yang
{"title":"Tuning the ferroelectricity of Hf0.5Zr0.5O2 with alloy electrodes","authors":"Keqin Liu, Bingjie Dang, Zhiyu Yang, Teng Zhang, Zhen Yang, Jinxuan Bai, Zelun Pan, Ru Huang, Yuchao Yang","doi":"10.1007/s11432-023-3932-2","DOIUrl":"https://doi.org/10.1007/s11432-023-3932-2","url":null,"abstract":"<p>Tuning ferroelectricity of Hf<sub>0.5</sub>Zr<sub>0.5</sub>O<sub>2</sub> is crucial for facilitating its practical applications in various fields, including in-memory and neuromorphic computing. Previous studies have revealed that the electrodes have a significant influence on ferroelectricity, and changing electrode materials can realize different but discrete ferroelectric polarization values. Here, we introduce an alloy-electrode method, in order to achieve gradual and accurate modulation of ferroelectric polarization, especially useful for matching the polarization charges at the interface of ferroelectric insulators and ferroelectric semiconductors. Au and W electrodes are chosen as baselines for realizing weak and strong ferroelectric polarization, where the intermediate states can be achieved by adjusting the ratio of metals in the Au-W alloy. To demonstrate the generality of this approach, the Cu-W alloy electrode is also realized for tuning ferroelectric polarization. The effect of alloy electrodes on device leakage current, endurance, and retention is evaluated. In addition, the temperature stability of ferroelectric capacitors is tested, where limited changes in both remnant polarization and coercive voltages are observed, showing the great potential of the ferroelectric hafnium oxide. Such gradual modulation of ferroelectric polarization could facilitate the application of Hf<sub>0.5</sub>Zr<sub>0.5</sub>O<sub>2</sub> in in-memory and neuromorphic computing.</p>","PeriodicalId":21618,"journal":{"name":"Science China Information Sciences","volume":null,"pages":null},"PeriodicalIF":8.8,"publicationDate":"2024-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141740295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Haoran Wu, Kaiming Nie, Jiangtao Xu, Qinglong Lin, Yingying Jiao
{"title":"A column-shared histogramming TDC with pixel-to-pixel coincidence detection and compact analog counters for Flash LiDAR sensor","authors":"Haoran Wu, Kaiming Nie, Jiangtao Xu, Qinglong Lin, Yingying Jiao","doi":"10.1007/s11432-024-4079-x","DOIUrl":"https://doi.org/10.1007/s11432-024-4079-x","url":null,"abstract":"<p>This study presents a column-shared hTDC with pixel-to-pixel coincidence detection and compact analog pulse counters. The column-shared architecture allows the hTDC to have no large area consumption caused by ADC and memories in pixels. Thanks to the pixel-to-pixel coincidence detection, only one SPAD is needed in each pixel. The application of the analog counter greatly reduces the area occupied by the counter. The simulation results show that the proposed hTDC can effectively reduce the pixel area while ensuring accuracy under high background light conditions, so it is suitable for outdoor applications.</p>","PeriodicalId":21618,"journal":{"name":"Science China Information Sciences","volume":null,"pages":null},"PeriodicalIF":8.8,"publicationDate":"2024-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141611831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"State estimation for delayed switched positive systems: delayed radius approach","authors":"Weizhong Chen, Zhongyang Fei, Xudong Zhao, Zheng-Guang Wu","doi":"10.1007/s11432-023-3980-0","DOIUrl":"https://doi.org/10.1007/s11432-023-3980-0","url":null,"abstract":"<p>In this paper, an interval estimation scheme is developed for delayed switched positive systems (DSPS) with mode-dependent average dwell time switching. A lossless zonotopic estimation approach is proposed for the delayed intersection zonotope with the positive generator matrix. First, considering the existence of asynchronism between the system mode and the correction matrix mode, the mismatched intersection zonotope is constructed for DSPS to verify the consistency between the system model and outputs. Then, by utilizing the introduced radius definitions, the <i>ℓ</i><sub>∞</sub> performance is addressed to optimize the size of delayed intersection zonotopes. Subsequently, we present a joint-design approach of switching signals and the mode-dependent correction matrix by constructing positive generator matrix-based delayed radius functions. Furthermore, guaranteed nonnegative state bounds are derived for the considered DSPS based on the proposed lossless zonotopic estimation criteria. Finally, detailed simulations are conducted to validate the feasibility and superiority of the developed methods.</p>","PeriodicalId":21618,"journal":{"name":"Science China Information Sciences","volume":null,"pages":null},"PeriodicalIF":8.8,"publicationDate":"2024-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141784756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"HEN: a novel hybrid explainable neural network based framework for robust network intrusion detection","authors":"Wei Wei, Sijin Chen, Cen Chen, Heshi Wang, Jing Liu, Zhongyao Cheng, Xiaofeng Zou","doi":"10.1007/s11432-023-4067-x","DOIUrl":"https://doi.org/10.1007/s11432-023-4067-x","url":null,"abstract":"<p>With the rapid development of network technology and the automation process for 5G, cyber-attacks have become increasingly complex and threatening. In response to these threats, researchers have developed various network intrusion detection systems (NIDS) to monitor network traffic. However, the incessant emergence of new attack techniques and the lack of system interpretability pose challenges to improving the detection performance of NIDS. To address these issues, this paper proposes a hybrid explainable neural network-based framework that improves both the interpretability of our model and the performance in detecting new attacks through the innovative application of the explainable artificial intelligence (XAI) method. We effectively introduce the Shapley additive explanations (SHAP) method to explain a light gradient boosting machine (LightGBM) model. Additionally, we propose an autoencoder long-term short-term memory (AE-LSTM) network to reconstruct SHAP values previously generated. Furthermore, we define a threshold based on reconstruction errors observed during the training phase. Any network flow that surpasses the specified threshold is classified as an attack flow. This approach enhances the framework’s ability to accurately identify attacks. We achieve an accuracy of 92.65%, a recall of 95.26%, a precision of 92.57%, and an F1-score of 93.90% on the dataset NSL-KDD. Experimental results demonstrate that our approach generates detection performance on par with state-of-the-art methods.</p>","PeriodicalId":21618,"journal":{"name":"Science China Information Sciences","volume":null,"pages":null},"PeriodicalIF":8.8,"publicationDate":"2024-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141515954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}