A 10-GS/s 8-bit 2× time interleaved hybrid ADC with λ/4 reference T-Line sharing technique

A 10-GS/s 8-bit 2× time interleaved hybrid ADC with λ/4 reference T-Line sharing technique has been demonstrated. Meanwhile, an on-chip 5th HILO with a center frequency of 20 GHz is embedded to generate the low-jitter propagation signal for T-Lines. The proposed sharing reference T-Line technique and serpentine routing enable a significant improvement on silicon-area efficiency. The ADC achieves a measured 3-dB effective bandwidth close to 6.7 GHz and an ENOB exceeding 5.5. The hybrid ADC chip fabricated in 0.9-V 28-nm CMOS achieves a 10-GS/s sampling frequency with a 31.22-mW power consumption. At Nyquist input, the SNDR is 38.11 dB, while at over-Nyquist 7.89 GHz input, the SNDR is 34.2 dB.