基于 DAC-DSP 的 56 Gb/s 发射器,采用基于反 PR 的 PD 进行自适应重定时时钟优化,在 28-nm CMOS 中实现 8-UI 收敛时间

IF 7.3 2区 计算机科学 Q1 COMPUTER SCIENCE, INFORMATION SYSTEMS
Shubin Liu, Chenxi Han, Xiaoteng Zhao, Yuhao Zhang, Shixin Li, Hongzhi Liang, Lihong Yang, Zhangming Zhu
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引用次数: 0

摘要

这项工作为 TX 提出了一种自适应时钟优化方案,以减轻重定时器的时序限制。利用基于 PR 和反 PR 的相位检测器,选择最佳时钟相位进行重定时,收敛时间仅为 8 UI。通过采用所提出的技术,我们在 28-nm CMOS 中实现了基于 DAC-DSP 的 1-56 Gb/s TX。测量结果表明,相位调整完成时,重定时时钟的上升沿位于数据的中心。整个 TX 在 0.25 平方毫米的面积内消耗 164 mWat 56-Gb/s PAM4 信号,RLM 为 97.8%。因此,所提出的重定时时钟优化方案是一种很有前途的高速 TX 方案。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 56 Gb/s DAC-DSP-based transmitter with adaptive retiming clock optimization using inverse-PR-based PD achieving 8-UI converge time in 28-nm CMOS

This work presents an adaptive clock optimization scheme for TX to alleviate the timing constraints for the retimer. Using the PR and inverse-PR-based phase detector, the optimal clock phase is selected for retiming with only 8 UI convergence time. By adopting the proposed technique, we realize a 1–56 Gb/s DAC-DSP-based TX in 28-nm CMOS. Measurement results show that the rising edge of retiming clock is located in the center of data when the phase adjustment completed. The total TX consumes 164 mWat 56-Gb/s PAM4 signaling with 97.8% RLM in 0.25 mm2 area. Therefore, the proposed retiming clock optimization scheme is a promising scheme for high-speed TX.

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来源期刊
Science China Information Sciences
Science China Information Sciences COMPUTER SCIENCE, INFORMATION SYSTEMS-
CiteScore
12.60
自引率
5.70%
发文量
224
审稿时长
8.3 months
期刊介绍: Science China Information Sciences is a dedicated journal that showcases high-quality, original research across various domains of information sciences. It encompasses Computer Science & Technologies, Control Science & Engineering, Information & Communication Engineering, Microelectronics & Solid-State Electronics, and Quantum Information, providing a platform for the dissemination of significant contributions in these fields.
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