Proceedings of the 2018 on Great Lakes Symposium on VLSI最新文献_第5页

Mixed-Signal POp/J Computing with Nonvolatile Memories 非易失性存储器的混合信号POp/J计算

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194612

M. Mahmoodi, D. Strukov

引用次数: 1

Accelerating Coverage Directed Test Generation for Functional Verification: A Neural Network-based Framework 加速功能验证的覆盖导向测试生成:一个基于神经网络的框架

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194561

Fanchao Wang, Hanbin Zhu, Pranjay Popli, Yao Xiao, P. Bogdan, Shahin Nazarian

{"title":"Accelerating Coverage Directed Test Generation for Functional Verification: A Neural Network-based Framework","authors":"Fanchao Wang, Hanbin Zhu, Pranjay Popli, Yao Xiao, P. Bogdan, Shahin Nazarian","doi":"10.1145/3194554.3194561","DOIUrl":"https://doi.org/10.1145/3194554.3194561","url":null,"abstract":"With increasing design complexity, the correlation between test transactions and functional properties becomes non-intuitive, hence impacting the reliability of test generation. This paper presents a modified coverage directed test generation based on an Artificial Neural Network (ANN). The ANN extracts features of test transactions and only those which are learned to be critical, will be sent to the design under verification. Furthermore, the priority of coverage groups is dynamically learned based on the previous test iterations. With ANN-based screening, low-coverage or redundant assertions will be filtered out, which helps accelerate the verification process. This allows our framework to learn from the results of the previous vectors and use that knowledge to select the following test vectors. Our experimental results confirm that our learning-based framework can improve the speed of existing function verification techniques by 24.5x and also also deliver assertion coverage improvement, ranging from 4.3x to 28.9x, compared to traditional coverage directed test generation, implemented in UVM.","PeriodicalId":215940,"journal":{"name":"Proceedings of the 2018 on Great Lakes Symposium on VLSI","volume":"187 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114970409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20

Low Complexity Burst Error Correcting Codes to Correct MBUs in SRAMs 低复杂度突发纠错码对ram中MBUs的纠错

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194570

Abhishek Das, N. Touba

{"title":"Low Complexity Burst Error Correcting Codes to Correct MBUs in SRAMs","authors":"Abhishek Das, N. Touba","doi":"10.1145/3194554.3194570","DOIUrl":"https://doi.org/10.1145/3194554.3194570","url":null,"abstract":"Multiple bit upsets (MBUs) caused by high energy radiation is the most common source of soft errors in static random-access memories (SRAMs) affecting multiple cells. Burst error correcting Hamming codes have most commonly been used to correct MBUs in SRAM cell since they have low redundancy and low decoder latency. But with technology scaling, the number of bits being affected increases, thus requiring a need for increasing the burst size that can be corrected. However, this is a problem because it increases the number of syndromes exponentially thus increasing the decoder complexity exponentially as well. In this paper, a new burst error correcting code based on Hamming codes is proposed which allows much better scaling of decoder complexity as the burst size is increased. For larger burst sizes, it can provide significantly smaller and faster decoders than existing methods thus providing higher reliability at an affordable cost. Moreover, there is frequently no increase in the number of check bits or a very minimal increase in comparison with existing methods. A general construction and decoding methodology for the new codes is proposed. Experimental results are presented comparing the decoder complexity for the proposed codes with conventional burst error correcting Hamming codes demonstrating the significant improvements that can be achieved.","PeriodicalId":215940,"journal":{"name":"Proceedings of the 2018 on Great Lakes Symposium on VLSI","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128569276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Cross-Lock: Dense Layout-Level Interconnect Locking using Cross-bar Architectures 交叉锁:密集布局级互连锁使用交叉条架构

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194580

Kaveh Shamsi, Meng Li, D. Pan, Yier Jin

引用次数: 39

Simultaneous Timing Driven Tree Surgery in Routing with Machine Learning-based Acceleration

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194556

Peishan Tu, Chak-Wa Pui, Evangeline F. Y. Young

引用次数: 0

Low-Power Optical Interconnects based on Resonant Silicon Photonic Devices: Recent Advances and Challenges 基于谐振硅光子器件的低功耗光互连:最新进展与挑战

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194606

M. Bahadori, K. Bergman

引用次数: 8

Design Space Exploration of Magnetic Tunnel Junction based Stochastic Computing in Deep Learning 基于深度学习随机计算的磁隧道结设计空间探索

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194619

You Wang, Yue Zhang, Youguang Zhang, Weisheng Zhao, Hao Cai, L. Naviner

{"title":"Design Space Exploration of Magnetic Tunnel Junction based Stochastic Computing in Deep Learning","authors":"You Wang, Yue Zhang, Youguang Zhang, Weisheng Zhao, Hao Cai, L. Naviner","doi":"10.1145/3194554.3194619","DOIUrl":"https://doi.org/10.1145/3194554.3194619","url":null,"abstract":"Magnetic tunnel junction (MTJ) is considered as a promising memory candidate in the more than Moore era because of high power efficiency, fast access speed, nearly infinite endurance and easy 3D integration. The nondeterministic switching behavior has been profited to exploit new directions for computing methods, such as stochastic computing. In this paper, the application of stochastic switching behavior in stochastic computing is explored for deep neural network (DNN). Stochastic computing method features low logic complexity, low energy consumption and fine-grained parallelism, boosting the performance of DNN system by combining MTJ. As a key block of stochastic computing, MTJ based true random number generator design is presented in details. The functionality has been validated by combining the hardware design and post-processing in software. Simulation results are demonstrated visibly by handwritten digits recognition test to show the accuracy. Furthermore, the performance is investigated in terms of accuracy, energy consumption and memory occupation to find more efficient techniques.","PeriodicalId":215940,"journal":{"name":"Proceedings of the 2018 on Great Lakes Symposium on VLSI","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127276411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

On the Design of Reliable Heterogeneous Systems via Checkpoint Placement and Core Assignment 基于检查点布置和核心分配的可靠异构系统设计

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194642

E. Sha, Hailiang Dong, Weiwen Jiang, Qingfeng Zhuge, Xianzhang Chen, Lei Yang

{"title":"On the Design of Reliable Heterogeneous Systems via Checkpoint Placement and Core Assignment","authors":"E. Sha, Hailiang Dong, Weiwen Jiang, Qingfeng Zhuge, Xianzhang Chen, Lei Yang","doi":"10.1145/3194554.3194642","DOIUrl":"https://doi.org/10.1145/3194554.3194642","url":null,"abstract":"This paper studies two basic problems in the design of high-performance and high-reliability heterogeneous systems: (1) what type of core to execute each task, and (2) where to place checkpoints in the execution of tasks. The implementation of checkpointing techniques on the novel persistent memory (e.g., 3D Xpoint memory) based heterogeneous systems faces a bundle of new problems. First, the assignments of tasks may greatly influence the execution time of the whole application. Therefore, with the same time constraint, the reliability of the resultant system can be significantly affected. Second, creating checkpoints will incur heavy writes on persistent memories and reduce the lifetime of devices. In this paper, we optimally construct reliable systems by assigning tasks to the most suitable cores and placing minimum number of checkpoints in the application, such that the resultant system can satisfy the time constraint in the presence of faults. We devise an efficient dynamic programming algorithm to obtain the optimal assignment and checkpoint placement. Experimental results demonstrate that, compared with existing approaches, our technique can achieve 44% reductions on the number of checkpoints on average.","PeriodicalId":215940,"journal":{"name":"Proceedings of the 2018 on Great Lakes Symposium on VLSI","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129739801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Impolite High Speed Interfaces with Asynchronous Pulse Logic 不礼貌的高速接口异步脉冲逻辑

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194592

Merritt Miller, Carrie Segal, D. McCarthy, Aditya Dalakoti, Prashansa Mukim, F. Brewer

引用次数: 0

SimTRaX

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194650

K. Shkurko, Tim Grant, E. Brunvand, Daniel Kopta, J. Spjut, Elena Vasiou, Ian Mallett, Cem Yuksel

引用次数: 5