不礼貌的高速接口异步脉冲逻辑

Merritt Miller, Carrie Segal, D. McCarthy, Aditya Dalakoti, Prashansa Mukim, F. Brewer
{"title":"不礼貌的高速接口异步脉冲逻辑","authors":"Merritt Miller, Carrie Segal, D. McCarthy, Aditya Dalakoti, Prashansa Mukim, F. Brewer","doi":"10.1145/3194554.3194592","DOIUrl":null,"url":null,"abstract":"We present a design solution that allows design of higher-than-core rate operation with techniques that avoid PLL/DLL blocks to provide higher speed timing. Many modern integrated circuits (ICs) have high speed interfaces which operate at higher cycle rates than the core of the IC. As a result of the higher-than-core rate, these interfaces are not directly representable in the core sequential logic. Asynchronous pulse logic offers an alternative design method for high speed interfaces with similar performance, simpler circuitry and without resorting to high-power logic cells such as emitter coupled logic. Formal and practical considerations for constructing high-speed interfaces are described. Gate designs and timing information for example cases are presented. These cases suggest that 80% improvements on rate compared traditional clocked logic are possible.","PeriodicalId":215940,"journal":{"name":"Proceedings of the 2018 on Great Lakes Symposium on VLSI","volume":"95 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Impolite High Speed Interfaces with Asynchronous Pulse Logic\",\"authors\":\"Merritt Miller, Carrie Segal, D. McCarthy, Aditya Dalakoti, Prashansa Mukim, F. Brewer\",\"doi\":\"10.1145/3194554.3194592\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present a design solution that allows design of higher-than-core rate operation with techniques that avoid PLL/DLL blocks to provide higher speed timing. Many modern integrated circuits (ICs) have high speed interfaces which operate at higher cycle rates than the core of the IC. As a result of the higher-than-core rate, these interfaces are not directly representable in the core sequential logic. Asynchronous pulse logic offers an alternative design method for high speed interfaces with similar performance, simpler circuitry and without resorting to high-power logic cells such as emitter coupled logic. Formal and practical considerations for constructing high-speed interfaces are described. Gate designs and timing information for example cases are presented. These cases suggest that 80% improvements on rate compared traditional clocked logic are possible.\",\"PeriodicalId\":215940,\"journal\":{\"name\":\"Proceedings of the 2018 on Great Lakes Symposium on VLSI\",\"volume\":\"95 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-05-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 2018 on Great Lakes Symposium on VLSI\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/3194554.3194592\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2018 on Great Lakes Symposium on VLSI","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/3194554.3194592","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

我们提出了一种设计解决方案,允许设计高核速率的操作,避免了PLL/DLL块的技术,以提供更高的速度定时。许多现代集成电路(IC)具有高速接口,其工作周期速率高于IC的核心。由于高于核心速率,这些接口不能在核心顺序逻辑中直接表示。异步脉冲逻辑为高速接口提供了另一种设计方法,具有相似的性能,更简单的电路,而无需诉诸高功率逻辑单元,如发射极耦合逻辑。描述了构造高速接口的形式和实际考虑。给出了栅极设计和时序信息的实例。这些实例表明,与传统的时钟逻辑相比,该方法可以提高80%的速率。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Impolite High Speed Interfaces with Asynchronous Pulse Logic
We present a design solution that allows design of higher-than-core rate operation with techniques that avoid PLL/DLL blocks to provide higher speed timing. Many modern integrated circuits (ICs) have high speed interfaces which operate at higher cycle rates than the core of the IC. As a result of the higher-than-core rate, these interfaces are not directly representable in the core sequential logic. Asynchronous pulse logic offers an alternative design method for high speed interfaces with similar performance, simpler circuitry and without resorting to high-power logic cells such as emitter coupled logic. Formal and practical considerations for constructing high-speed interfaces are described. Gate designs and timing information for example cases are presented. These cases suggest that 80% improvements on rate compared traditional clocked logic are possible.
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