Proceedings of the 2018 on Great Lakes Symposium on VLSI最新文献

{"title":"A CMOS Low Power 4th-Order Delta-Sigma Modulator with One Reconfigurable Amplifier","authors":"Jae-hyeon Sung, K. Yoon","doi":"10.1145/3194554.3194641","DOIUrl":"https://doi.org/10.1145/3194554.3194641","url":null,"abstract":"This paper describes the 4th-order feedback delta-sigma modulator with only one reconfigurable amplifier. The modulator is designed with 180nm CMOS standard process. The measurement results demonstrate the power dissipation of 352uW, peak SNDR of 82.41dB and the ENOB of 13.4bits with an input signal frequency of 250Hz, a sampling frequency of 128 kHz, an input signal bandwidth of 1kHz, and an oversampling rate of 64.","PeriodicalId":215940,"journal":{"name":"Proceedings of the 2018 on Great Lakes Symposium on VLSI","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124264863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Silicon Photonic Interconnects: Minimizing the Controller Latency","authors":"F. Magalhães, M. Nikdast, Y. Xiong, Fabiano Hessel, O. Liboiron-Ladouceur, G. Nicolescu","doi":"10.1145/3194554.3194609","DOIUrl":"https://doi.org/10.1145/3194554.3194609","url":null,"abstract":"Silicon photonic interconnects (SPIs) have emerged as a promising solution to outperform the communication infrastructure in multiprocessor systems-on-chip (MPSoCs). Routing a message from one node to another in an MPSoC integrating SPIs, several photonic components (e.g., switching elements) need to be configured to realize an optical path between sending and receiving nodes. Such configurations are performed in an electronic controller, which, if not fast, imposes high latency in SPIs, constraining the application of SPIs in MPSoCs. Realizing a full exploitation of SPIs, this paper presents a look-up-table-based centralized controller (LUCC). We indicate that LUCC has the lowest latency among the state-of-the-art controllers for SPIs while it can be applied to different SPI architectures. Employing acceleration techniques based on off-line routings, we report (simulation and prototyping) a worst-case control latency smaller than 5 ns. Moreover, LUCC is experimentally integrated with a photonic switch in the lab, where we show contention resolution in one clock cycle.","PeriodicalId":215940,"journal":{"name":"Proceedings of the 2018 on Great Lakes Symposium on VLSI","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123768512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Self-Awareness for Heterogeneous MPSoCs: A Case Study using Adaptive, Reflective Middleware","authors":"N. Dutt","doi":"10.1145/3194554.3200203","DOIUrl":"https://doi.org/10.1145/3194554.3200203","url":null,"abstract":"Self-awareness has a long history in biology, psychology, medicine, engineering and (more recently) computing. In the past decade this has inspired new self-aware strategies for emerging computing substrates (e.g., complex heterogeneous MPSoCs) that must cope with the (often conflicting) challenges of resiliency, energy, heat, cost, performance, security, etc. in the face of highly dynamic operational behaviors and environmental conditions. Earlier we had championed the concept of CyberPhysical-Systems-on-Chip (CPSoC), a new class of sensor-actuator rich many-core computing platforms that intrinsically couples on-chip and cross-layer sensing and actuation to enable self-awareness. Unlike traditional MPSoCs, CPSoC is distinguished by an intelligent co-design of the control, communication, and computing (C3) system that interacts with the physical environment in real-time in order to modify the system's behavior so as to adaptively achieve desired objectives and Quality-of-Service (QoS). The CPSoC design paradigm enables self-awareness (i.e., the ability of the system to observe its own internal and external behaviors such that it is capable of making judicious decision) and (opportunistic) adaptation using the concept of cross-layer physical and virtual sensing and actuations applied across different layers of the hardware/software system stack. The closed loop control used for adaptation to dynamic variation -- commonly known as the observe-decide-act (ODA) loop -- is implemented using an adaptive, reflective middleware layer. In this talk I will present a case study of this adaptive, reflective middleware layer using a holistic approach for performing resource allocation decisions and power management by leveraging concepts from reflective software. Reflection enables dynamic adaptation based on both external feedback and introspection (i.e., self-assessment). In our context, this translates into performing resource management actuation considering both sensing information (e.g., readings from performance counters, power sensors, etc.) to assess the current system state, as well as models to predict the behavior of other system components before performing an action. I will summarize results leveraging our adaptive-reflective middleware toolchain to i) perform energy-efficient task mapping on heterogeneous architectures, ii) explore the design space of novel HMP architectures, and iii) extend the lifetime of mobile devices.","PeriodicalId":215940,"journal":{"name":"Proceedings of the 2018 on Great Lakes Symposium on VLSI","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124500368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Interfacing 3D-stacked Electronic and Optical NoCs with Mixed CMOS-ECL Bridges: a Realistic Preliminary Assessment","authors":"Mahdi Tala, O. Schrape, M. Krstic, D. Bertozzi","doi":"10.1145/3194554.3194593","DOIUrl":"https://doi.org/10.1145/3194554.3194593","url":null,"abstract":"The combination of optical networks-on-chip and 3D stacking represents the most promising system integration framework to overcome the communication bottleneck of future many-core processors. From an architecture viewpoint, the availability of an energy-efficient, low-latency bridge connecting the electronic network-on-chip with the optical one is as important as the maturity of the optical interconnect technology. The key design challenge consists of overcoming the inherent serial nature of optical communications, which is typically pursued by increasing either the data rate or the bit-level parallelism, or by a combination thereof. This paper explores an hybrid CMOS-ECL technology platform for bridge implementation by means of a complete logic synthesis effort. By spanning the wider configuration space of the hybrid bridge with respect to fully-CMOS realizations, the paper identifies the most energy-efficient configurations and provides a comparative assessment of achievable quality metrics. Derived results represent a solid and realistic starting point for future optimizations and for the refinement into an actual layout.","PeriodicalId":215940,"journal":{"name":"Proceedings of the 2018 on Great Lakes Symposium on VLSI","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124042795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Physical Protection of Lattice-Based Cryptography: Challenges and Solutions","authors":"A. Khalid, Tobias Oder, Felipe Valencia, Máire O’Neill, T. Güneysu, F. Regazzoni","doi":"10.1145/3194554.3194616","DOIUrl":"https://doi.org/10.1145/3194554.3194616","url":null,"abstract":"The impending realization of scalable quantum computers will have a significant impact on today's security infrastructure. With the advent of powerful quantum computers public key cryptographic schemes will become vulnerable to Shor's quantum algorithm, undermining the security current communications systems. Post-quantum (or quantum-resistant) cryptography is an active research area, endeavoring to develop novel and quantum resistant public key cryptography. Amongst the various classes of quantum-resistant cryptography schemes, lattice-based cryptography is emerging as one of the most viable options. Its efficient implementation on software and on commodity hardware has already been shown to compete and even excel the performance of current classical security public-key schemes. This work discusses the next step in terms of their practical deployment, i.e., addressing the physical security of lattice-based cryptographic implementations. We survey the state-of-the-art in terms of side channel attacks (SCA), both invasive and passive attacks, and proposed countermeasures. Although the weaknesses exposed have led to countermeasures for these schemes, the cost, practicality and effectiveness of these on multiple implementation platforms, however, remains under-studied.","PeriodicalId":215940,"journal":{"name":"Proceedings of the 2018 on Great Lakes Symposium on VLSI","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125779025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Performance Impact of Emerging Memory Technologies on Big Data Applications: A Latency-Programmable System Emulation Approach","authors":"Mu-Tien Chang, I. Choi, Dimin Niu, Hongzhong Zheng","doi":"10.1145/3194554.3194633","DOIUrl":"https://doi.org/10.1145/3194554.3194633","url":null,"abstract":"This paper presents a performance analysis framework for studying emerging memories. The key component of the framework is a memory-latency programmable emulator, which is based on a FPGA-attached server system. The emulator allows users extend read and/or write latency. In addition, we use regression models to enable system performance studies for memory latencies beyond hardware limitations. Finally, we demonstrate Spark application case studies, analyzing the impact of two key characteristics of emerging memories: extended memory access times and enlarged memory capacities. Results show that the benefit of high capacity memory could outweigh the performance loss due to longer memory latency.","PeriodicalId":215940,"journal":{"name":"Proceedings of the 2018 on Great Lakes Symposium on VLSI","volume":"380 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132032808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Hardware Assurance: Trojans, Counterfeits, and Security in an Interconnected World","authors":"M. Casto","doi":"10.1145/3194554.3194555","DOIUrl":"https://doi.org/10.1145/3194554.3194555","url":null,"abstract":"Dr. Matthew Casto is Chief of the Air Force Research Laboratory, Sensor’s Directorate, Trusted Electronics Branch. He is the Air Force’s Hardware Assurance technical lead for the Department of Defense (DoD) Joint Federated Assurance Center, and the Science and Technology technical execution lead for the DoD Trusted and Assured Microelectronics Initiative. Dr. Casto is a Senior Electronics Engineer with a BSEE and MSEE degree from Wright State University, and a PhD from The Ohio State University Electro-science Laboratory. Matt is a member of the IEEE and has authored numerous publications and patents in the areas of nonlinear and electro-thermal device modeling, advanced mixedsignal integrated circuit, system on a chip, design and characterization, and the design and analysis of secure, trustworthy microelectronics.","PeriodicalId":215940,"journal":{"name":"Proceedings of the 2018 on Great Lakes Symposium on VLSI","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132108063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Securing the Systems of the Future - Techniques for a Shifting Attack Space","authors":"I. Savidis, S. Bhunia, G. Qu, M. Casto, J. Muldavin","doi":"10.1145/3194554.3216447","DOIUrl":"https://doi.org/10.1145/3194554.3216447","url":null,"abstract":"Panel Overview Known security vulnerabilities across the computing stack have caused significant concern, even requiring extensive countermeasures and system patches to address. As an example, the Meltdown and Spectre attacks, which were disclosed in January 2018, exploit architectural and circuit vulnerabilities to allow a malicious process access to secrets stored in the memory of another running program. Although software-based patches were distributed, true hardware solutions are only available through replacement. With such high costs to protect data and patch systems after the fact, the question of securing against an unknown attack space becomes even more critical. The panel aims to address this critical issue, while introducing related considerations including 1) protecting resource constrained systems, 2) countermeasures against multifaceted attacks in the context of an unknown future vulnerability, and 3) trade-offs in circuit and system design to protect critical data and functions.","PeriodicalId":215940,"journal":{"name":"Proceedings of the 2018 on Great Lakes Symposium on VLSI","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131446866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"TaSaT","authors":"Mohamad Hammam Alsafrjalani, Tosiron Adegbija","doi":"10.1145/3194554.3194576","DOIUrl":"https://doi.org/10.1145/3194554.3194576","url":null,"abstract":"Heterogeneous and configurable systems (HaCS) have been widely used to meet stringent runtime performance and energy constraints in embedded systems. However, no prior work has addressed the emerging runtime thermal constraints in these systems. To leverage HaCS' capabilities to meet thermal constraints, in addition to performance and energy constraints, we propose TaSaT, a Thermal-aware Scheduling and Tuning algorithm for HaCS. TaSaT reduces HaCS temperature while meeting performance and energy constraints during runtime, without a priori knowledge of applications.","PeriodicalId":215940,"journal":{"name":"Proceedings of the 2018 on Great Lakes Symposium on VLSI","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124544770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Towards A Universal Power Manager for Multi-Source Energy Scavenging and Storage","authors":"S. Mazumder","doi":"10.1145/3194554.3194604","DOIUrl":"https://doi.org/10.1145/3194554.3194604","url":null,"abstract":"Power efficiency of multi-source integrated energy harvesting (EH), storage, and delivery is a fundamental requirement of emerging energy autonomous internet-of-thing (IoT) and internet-of-everything (IoE) devices. To make these energy autonomous devices practical, an enhanced, universal power management integrated circuit (PMIC) needs to be developed for efficiently controlling power on-chip. Currently, there exists no universal power manager (UPM) that seamlessly interfaces to DC and/or AC EH sources. The state of the art viable PMICs delivered by industry rely primarily on the following approach: for an unregulated DC source a DC/DC power manager is adopted whereas for an AC source, a front-end rectifier is inserted. This reduces efficiency and enhances distortion, requiring additional filtering.","PeriodicalId":215940,"journal":{"name":"Proceedings of the 2018 on Great Lakes Symposium on VLSI","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114805701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}