Proceedings of the 2018 on Great Lakes Symposium on VLSI最新文献_第2页

Design of Dynamic Range Approximate Logarithmic Multipliers 动态范围近似对数乘法器的设计

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194628

Peipei Yin, Chenghua Wang, Weiqiang Liu, F. Lombardi

引用次数: 4

A Homomorphic Encryption Scheme Based on Affine Transforms 基于仿射变换的同态加密方案

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194585

Kyle Loyka, He Zhou, S. Khatri

{"title":"A Homomorphic Encryption Scheme Based on Affine Transforms","authors":"Kyle Loyka, He Zhou, S. Khatri","doi":"10.1145/3194554.3194585","DOIUrl":"https://doi.org/10.1145/3194554.3194585","url":null,"abstract":"As more businesses and consumers move their information storage to the cloud, the need to protect sensitive data is higher than ever. Using encryption, data access can be restricted to only authorized users. However, with standard encryption schemes, modifying an encrypted file in the cloud requires a complete file download, decryption, modification, and upload. This is cumbersome and time-consuming. Recently, the concept of homomorphic computing has been proposed as a solution to this problem. Using homomorphic computation, operations may be performed directly on encrypted files without decryption, hence avoiding exposure of any sensitive user information in the cloud. This also conserves bandwidth and reduces processing time. In this paper, we present a homomorphic computation scheme that utilizes the affine cipher applied to the ASCII representation of data. To the best of the authors» knowledge, this is the first use of affine ciphers in homomorphic computing. Our scheme supports both string operations (encrypted string search and concatenation), as well as arithmetic operations (encrypted integer addition and subtraction). A design goal of our proposed homomorphism is that string data and integer data are treated identically, in order to enhance security.","PeriodicalId":215940,"journal":{"name":"Proceedings of the 2018 on Great Lakes Symposium on VLSI","volume":"307 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117156545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A Hybrid Approach to Equivalent Fault Identification for Verification Environment Qualification 验证环境鉴定中等效故障识别的混合方法

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194635

Chia-Cheng Wu, Tung-Yuan Lee, Yung-An Lai, Hsin-Pei Wang, De-Xuan Ji, Yan-Ping Chang, Teng-Chia Wang, Chin-Heng Liu, Chun-Yao Wang, Yung-Chih Chen

引用次数: 0

Energy and Area Efficiency in Neuromorphic Computing for Resource Constrained Devices 资源受限设备神经形态计算中的能量和面积效率

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194611

Gangotree Chakma, Nicholas D. Skuda, Catherine D. Schuman, J. Plank, Mark E. Dean, G. Rose

{"title":"Energy and Area Efficiency in Neuromorphic Computing for Resource Constrained Devices","authors":"Gangotree Chakma, Nicholas D. Skuda, Catherine D. Schuman, J. Plank, Mark E. Dean, G. Rose","doi":"10.1145/3194554.3194611","DOIUrl":"https://doi.org/10.1145/3194554.3194611","url":null,"abstract":"Resource constrained devices are the building blocks of the internet of things (IoT) era. Since the idea behind IoT is to develop an interconnected environment where the devices are tiny enough to operate with limited resources, several control systems have been built to maintain low energy and area consumption while operating as IoT edge devices. Several researchers have begun work on implementing control systems built from resource constrained devices using machine learning. However, there are many ways such devices can achieve lower power consumption and area utilization while maximizing application efficiency. Spiky neuromorphic computing (SNC) is an emerging paradigm that can be leveraged in resource constrained devices for several emerging applications. While delivering the benefits of machine learning, SNC also helps minimize power consumption. For example, low energy memory devices (memristors) are often used to achieve low power operation and also help in reducing system area. In total, we anticipate SNC will provide computational efficiency approaching that of deep learning while using low power, resource constrained devices.","PeriodicalId":215940,"journal":{"name":"Proceedings of the 2018 on Great Lakes Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129623216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

A Machine Learning Attack Resistant Dual-mode PUF 抗机器学习攻击的双模PUF

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194590

Qian Wang, Mingze Gao, G. Qu

{"title":"A Machine Learning Attack Resistant Dual-mode PUF","authors":"Qian Wang, Mingze Gao, G. Qu","doi":"10.1145/3194554.3194590","DOIUrl":"https://doi.org/10.1145/3194554.3194590","url":null,"abstract":"Silicon Physical Unclonable Function (PUF) is arguably the most promising hardware security primitive. In particular, PUFs that are capable of generating a large amount of challenge response pairs (CRPs) can be used in many security applications. However, these CRPs can also be exploited by machine learning attacks to model the PUF and predict its response. In this paper, we first show that, based on data in the public domain, two popular PUFs that can generate CRPs (i.e., arbiter PUF and reconfigurable ring oscillator (RO) PUF) can be broken by simple logistic regression (LR) attack with about 99% accuracy. We then propose a feedback structure to XOR the PUF response with the challenge and challenge the PUF again to generate the response. Results show that this successfully reduces LR's learning accuracy to the lower 50%, but artificial neural network (ANN) learning attack still has an 80% success rate. Therefore, we propose a configurable ring oscillator based dual-mode PUF which works with both odd number of inverters (like the reconfigurable RO PUF) and even number of inverters (like a bistable ring (BR) PUF). Since currently there are no known attacks that can model both RO PUF and BR PUF, the dual-mode PUF will be resistant to modeling attacks as long as we can hide its working mode from the attackers, which we achieve with two practical methods. Finally, we implement the proposed dual-mode PUF on Nexys 4 FPGA boards and collect real measurement to show that it reduces the learning accuracy of LR and ANN to the mid-50% and low 60%, respectively. In addition, it meets the PUF requirements of uniqueness, randomness, and robustness.","PeriodicalId":215940,"journal":{"name":"Proceedings of the 2018 on Great Lakes Symposium on VLSI","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122385410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 27

Session details: Special Session 5: Artificial Intelligence at the Edge 会议详情:特别会议5:边缘人工智能

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3252918

Cory E. Merkel, D. Kudithipudi

引用次数: 0

Towards Near-Data Processing of Compare Operations in 3D-Stacked Memory 3d堆叠存储器中比较运算的近数据处理

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194578

P. Das, H. Kapoor

{"title":"Towards Near-Data Processing of Compare Operations in 3D-Stacked Memory","authors":"P. Das, H. Kapoor","doi":"10.1145/3194554.3194578","DOIUrl":"https://doi.org/10.1145/3194554.3194578","url":null,"abstract":"The gap between the processing speed and memory access speed of the modern multi-core systems has become a bottleneck for the emerging data-intensive workloads. In this scenario, it has become a smarter idea to move some amount of computation closer to the data, thus stimulating the concept of near-data processing (NDP). Compare or scanning, the core operations of many applications, typically in a database, can leverage the benefits of NDP. We propose near-data compare unit (NDCU), a less-invasive hardware, that can be integrated with the existing ecosystem of the hybrid memory cube (HMC). While integrating NDCU, we have designed two full-system architectures, one is lighter NDP with no parallelism (NNP) and the second is NDP with vault level parallelism (NVLP). While the first architecture is more power and area efficient, the second one is very fast with negligible overheads. With the motive of carrying out scan operation, we have specifically implemented 'compare-n-hit', 'compare-n-count' and 'compare-n-max' operations on both row-store and column-store databases and found significant improvements over conventional CPU-based system. We get around 2.3x and 37x performance improvement in NNP and NVLP architectures respectively. In both the designs, we reduce the energy consumption by around 8x on an average.","PeriodicalId":215940,"journal":{"name":"Proceedings of the 2018 on Great Lakes Symposium on VLSI","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126810323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Reliable On-Chip Voltage Regulation for Sustainable and Compact IoT and Heterogeneous Computing Systems 可靠的片上电压调节可持续和紧凑的物联网和异构计算系统

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194602

Longfei Wang, Selçuk Köse

{"title":"Reliable On-Chip Voltage Regulation for Sustainable and Compact IoT and Heterogeneous Computing Systems","authors":"Longfei Wang, Selçuk Köse","doi":"10.1145/3194554.3194602","DOIUrl":"https://doi.org/10.1145/3194554.3194602","url":null,"abstract":"As an essential part of modern power delivery networks, on-chip voltage regulation consisting of multiple distributed voltage regulators provides the required power and voltage levels for localized load circuits. The harsh application environment of internet of things (IoT) and heterogeneous computing systems including, but not limited to, high temperature and large load current variations, can lead to significant and uneven performance degradations of on-chip voltage regulators due to aging. Investigating sustainable on-chip voltage regulation schemes considering the lifetime of different distributed voltage regulators becomes imperative. Furthermore, techniques to mitigate the aging induced voltage regulator degradations can consume the scarce on-chip area resource. In this work, a new reliable on-chip voltage regulation technique is explored to simultaneously mitigate the performance degradation and reduce the area cost of distributed on-chip voltage regulators to achieve sustainable and compact design and satisfy the needs of different IoT and heterogeneous computing systems considering the interactions among different regulators. A brief survey of reliable design challenges and potential solutions is also provided.","PeriodicalId":215940,"journal":{"name":"Proceedings of the 2018 on Great Lakes Symposium on VLSI","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130156201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Session details: Session 5: The World of Neural Networks 会议详情:第5部分:神经网络的世界

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3252912

A. Ganguly

引用次数: 0

Resilient AES Against Side-Channel Attack Using All-Spin Logic 使用全自旋逻辑抗侧信道攻击的弹性AES

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194595

Qutaiba Alasad, Jiann-Shiun Yuan, Jie Lin

引用次数: 8