Resilient AES Against Side-Channel Attack Using All-Spin Logic

Abstract

The new generation of spintronic devices, Hybrid Spintronic-CMOS devices including Magnetic Tunnel Junction (MTJ), have been utilized to overcome Moore's law limitation as well as preserve higher performance with lower cost. However, implementing these devices as a hardware cryptosystem is vulnerable to side channel attacks (SCAs) due to the differential power at the output of the Hybrid Spintronic-CMOS device and asymmetric read/write operations in MTJ. One of the most severe SCAs is the power analysis attack (PAA), in which an attacker can observe the output current of the device and extract the secret key. In this paper, we employ the All Spin Logic Device (ASLD) to implement protected AES cryptography for the first time. More precisely, we realize that in additional to ASLD features, such as small area, non-volatile memory, high density and low operating voltage, this device has another unique feature: identical power dissipation through the switching operations. Such properties can be effectively leveraged to prevent SCA.