{"title":"带一个可重构放大器的CMOS低功耗四阶Delta-Sigma调制器","authors":"Jae-hyeon Sung, K. Yoon","doi":"10.1145/3194554.3194641","DOIUrl":null,"url":null,"abstract":"This paper describes the 4th-order feedback delta-sigma modulator with only one reconfigurable amplifier. The modulator is designed with 180nm CMOS standard process. The measurement results demonstrate the power dissipation of 352uW, peak SNDR of 82.41dB and the ENOB of 13.4bits with an input signal frequency of 250Hz, a sampling frequency of 128 kHz, an input signal bandwidth of 1kHz, and an oversampling rate of 64.","PeriodicalId":215940,"journal":{"name":"Proceedings of the 2018 on Great Lakes Symposium on VLSI","volume":"132 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A CMOS Low Power 4th-Order Delta-Sigma Modulator with One Reconfigurable Amplifier\",\"authors\":\"Jae-hyeon Sung, K. Yoon\",\"doi\":\"10.1145/3194554.3194641\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes the 4th-order feedback delta-sigma modulator with only one reconfigurable amplifier. The modulator is designed with 180nm CMOS standard process. The measurement results demonstrate the power dissipation of 352uW, peak SNDR of 82.41dB and the ENOB of 13.4bits with an input signal frequency of 250Hz, a sampling frequency of 128 kHz, an input signal bandwidth of 1kHz, and an oversampling rate of 64.\",\"PeriodicalId\":215940,\"journal\":{\"name\":\"Proceedings of the 2018 on Great Lakes Symposium on VLSI\",\"volume\":\"132 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-05-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 2018 on Great Lakes Symposium on VLSI\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/3194554.3194641\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2018 on Great Lakes Symposium on VLSI","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/3194554.3194641","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A CMOS Low Power 4th-Order Delta-Sigma Modulator with One Reconfigurable Amplifier
This paper describes the 4th-order feedback delta-sigma modulator with only one reconfigurable amplifier. The modulator is designed with 180nm CMOS standard process. The measurement results demonstrate the power dissipation of 352uW, peak SNDR of 82.41dB and the ENOB of 13.4bits with an input signal frequency of 250Hz, a sampling frequency of 128 kHz, an input signal bandwidth of 1kHz, and an oversampling rate of 64.
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