Proceedings of the 2018 on Great Lakes Symposium on VLSI最新文献_第4页

AB-Aware: Application Behavior Aware Management of Shared Last Level Caches AB-Aware:共享最后一级缓存的应用程序行为感知管理

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194573

S. Pai, Newton Singh, Virendra Singh

{"title":"AB-Aware: Application Behavior Aware Management of Shared Last Level Caches","authors":"S. Pai, Newton Singh, Virendra Singh","doi":"10.1145/3194554.3194573","DOIUrl":"https://doi.org/10.1145/3194554.3194573","url":null,"abstract":"In modern multicore systems, Last-Level Cache (LLC) is usually shared among multiple cores. Though it benefits applications by sharing and utilizing cache resources efficiently; the benefits come at the cost of increased conflict misses due to interference among applications. In shared LLC, conventionally used LRU-based cache replacement policies logically partition the cache on-demand basis. Thus, cache friendly applications sharing LLC with streaming applications, suffer due to high data demands and low reuse of streaming applications. Apart from different data locality behavior, applications also show different memory access behavior while accessing the LLC. Some applications inherently have parallel memory accesses while others have more isolated long-latency accesses. The cost of idle cycles processor spends waiting for off-chip memory accesses is shared by parallel misses. However, misses which occur in isolation hurt the performance most. This adds another dimension to application's behavior. We propose an application behavior aware cache replacement policy to manage shared LLC. The proposed policy simultaneously reduces the negative interference among applications sharing the LLC and the miss-penalty associated with each LLC miss. Evaluation on SPEC CPU2006 benchmarks shows that our replacement policy improves performance on dual-core systems and quad-core system by up to 15.9% and 23.8% respectively over SRRIP for shared LLC. It is worth to note that effectiveness of our policy improves with the increase in the number of cores.","PeriodicalId":215940,"journal":{"name":"Proceedings of the 2018 on Great Lakes Symposium on VLSI","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131633575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A Cross-Layer Perspective for Energy Efficient Processing: - From beyond-CMOS Devices to Deep Learning 节能处理的跨层视角:从cmos器件到深度学习

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3200204

X. Hu

{"title":"A Cross-Layer Perspective for Energy Efficient Processing: - From beyond-CMOS Devices to Deep Learning","authors":"X. Hu","doi":"10.1145/3194554.3200204","DOIUrl":"https://doi.org/10.1145/3194554.3200204","url":null,"abstract":"As Moore's Law based device scaling and accompanying performance scaling trends are slowing down, there is increasing interest in new technologies and computational models for fast and more energy-efficient information processing. Meanwhile, there is growing evidence that, with respect to traditional Boolean circuits and von Neumann processors, it will be challenging for beyond-CMOS devices to compete with the CMOS technology. Nevertheless, some beyond-CMOS devices demonstrate other unique characteristics such as ambipolarity, negative differential resistance, hysteresis, and oscillatory behavior. Exploiting such unique characteristics, especially in the context of alternative circuit and architectural paradigms, has the potential to offer orders of magnitude improvement in terms of power, performance and capability. In order to take full advantage of beyond-CMOS devices, however, it is no longer sufficient to develop algorithms, architectures and circuits independent of one another. Cross-layer efforts spanning from devices to circuits to architectures to algorithms are indispensable. This talk will examine energy-efficient neural network accelerators for embedded applications in this context. Several deep neural network accelerator designs based on alternative device technologies, circuit styles and architectures will be highlighted. A comprehensive application-level benchmarking study for the MNIST dataset will be presented. The discussions will demonstrate that cross-layer efforts indeed can lead to orders of magnitude gain towards achieving extreme scale energy-efficient processing.","PeriodicalId":215940,"journal":{"name":"Proceedings of the 2018 on Great Lakes Symposium on VLSI","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131671618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A 0.24pJ/bit, 16Gbps OOK Transmitter Circuit in 45-nm CMOS for Inter and Intra-Chip Wireless Interconnects 一种0.24pJ/bit, 16Gbps的45纳米CMOS OOK发送电路，用于片内和片间无线互连

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194575

Tanmay Shinde, Suryanarayanan Subramaniam, Padmanabh Deshmukh, M. Ahmed, Mark A. Indovina, A. Ganguly

引用次数: 10

Short-path Padding Method for Timing Error Resilient Circuits based on Transmission Gates Insertion 基于传输门插入的时序误差弹性电路短路填充方法

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194600

Wentao Dai, Peiye Liu, Weiwei Shan

{"title":"Short-path Padding Method for Timing Error Resilient Circuits based on Transmission Gates Insertion","authors":"Wentao Dai, Peiye Liu, Weiwei Shan","doi":"10.1145/3194554.3194600","DOIUrl":"https://doi.org/10.1145/3194554.3194600","url":null,"abstract":"Resilient circuits based on timing error detection and correction can mitigate the timing margin effectively, but usually at a cost of extra area overhead. One of the major sources of area overhead is short-path padding (hold time fix), which is much severer than in traditional IC design for near-threshold operation. Therefore, we propose an insertion methodology by using transmission gates to extend short-paths, which decreases area overhead than traditional resilient methods. Because the clock-controlled transmission gate (CTG) can extend all the short paths by half a clock when working as a transparent-low latch, the short-paths problem is solved. Besides, as the transmission gates synchronize the multiple short paths, it decreases the invalid flipping of combinational logic, which reduces the glitch power. Applied on a SHA-256 algorithm circuit in a 28nm CMOS process with 0.55V supply, the proposed technique reduces the area overhead a lot compared to the conventional short-path padding techniques. For combinational circuit, its area reduces from 153.34% to 4.43%, and for sequential circuit area, it reduces from 124.33% to 19.33%.","PeriodicalId":215940,"journal":{"name":"Proceedings of the 2018 on Great Lakes Symposium on VLSI","volume":"171 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132325228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Electromigration Design Rule aware Global and Detailed Routing Algorithm 基于电迁移设计规则的全局详细路由算法

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194567

Xiaotao Jia, Jing Wang, Yici Cai, Qiang Zhou

引用次数: 0

A Novel Fault-Tolerant Last-Level Cache to Improve Reliability at Near-Threshold Voltage 一种提高近阈值电压下可靠性的新型容错最后级缓存

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194583

W. Liu, Zhigang Wei, Wei Du

引用次数: 1

DARPA's Data Driven Discovery of Models (D3M) and Software Defined Hardware (SDH) Programs DARPA的数据驱动模型发现(D3M)和软件定义硬件(SDH)计划

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3200206

Wade Shen

引用次数: 4

Static Design of Spin Transfer Torques Magnetic Look Up Tables for ASIC Designs 用于ASIC设计的自旋传递转矩磁表的静态设计

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194651

A. Attaran, T. Sheaves, Praveen Kumar Mugula, H. Mahmoodi

引用次数: 7

Session details: Special Session 1: Powering Heterogeneous IoT Systems: Design for Efficiency, Security and Sustainability 特别会议1:为异构物联网系统提供动力:效率、安全性和可持续性设计

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3252914

S. Kose, Inna Partin-Vaisband

引用次数: 0

Session details: Special Session 4: Implementing and Benchmarking Post-Quantum Cryptography in Hardware 专题会议4:后量子加密在硬件中的实现和基准测试

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3252917

K. Gaj

引用次数: 0