2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)最新文献

Skeleton-based design and simulation flow for Computation-in-Memory architectures 内存计算架构的基于骨架的设计和仿真流程

2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2016-09-14 DOI: 10.1145/2950067.2950071

Jintao Yu, R. Nane, Adib Haron, S. Hamdioui, H. Corporaal, K. Bertels

引用次数: 12

A memristor-based compressive sensing architecture 一种基于忆阻器的压缩感知结构

2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2016-07-18 DOI: 10.1145/2950067.2950081

F. Qian, Yanping Gong, Guoxian Huang, Kiarash Ahi, M. Anwar, Lei Wang

引用次数: 12

A novel circuit design of true random number generator using magnetic tunnel junction 一种基于磁隧道结的真随机数发生器电路设计

2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2016-07-18 DOI: 10.1145/2950067.2950108

You Wang, Hao Cai, L. Naviner, Jacques-Olivier Klein, Jianlei Yang, Weisheng Zhao

引用次数: 42

Sleep stage classification with stochastic Bayesian inference 基于随机贝叶斯推理的睡眠阶段分类

2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2016-07-18 DOI: 10.1145/2950067.2950085

L. Calvet, J. Friedman, D. Querlioz, P. Bessière, J. Droulez

引用次数: 2

Improved circuit model for all-spin logic 改进的全自旋逻辑电路模型

2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2016-07-18 DOI: 10.1145/2950067.2950075

M. Alawein, H. Fariborzi

引用次数: 5

Combining a volatile and nonvolatile memristor in artificial synapse to improve learning in Spiking Neural Networks 结合易失性与非易失性记忆电阻器在人工突触中改善脉冲神经网络的学习

2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2016-07-18 DOI: 10.1145/2950067.2950090

Mahyar Shahsavari, Pierre Falez, Pierre Boulet

引用次数: 18

Memory Processing Unit for in-memory processing 用于内存处理的内存处理单元

2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2016-07-18 DOI: 10.1145/2950067.2950086

Rotem Ben Hur, Shahar Kvatinsky

引用次数: 38

Exploring the optimal learning technique for IBM TrueNorth platform to overcome quantization loss 探索IBM TrueNorth平台克服量化损失的最佳学习技术

2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2016-07-18 DOI: 10.1145/2950067.2950096

Hsin-Pai Cheng, W. Wen, Chang Song, Beiye Liu, Hai Helen Li, Yiran Chen

{"title":"Exploring the optimal learning technique for IBM TrueNorth platform to overcome quantization loss","authors":"Hsin-Pai Cheng, W. Wen, Chang Song, Beiye Liu, Hai Helen Li, Yiran Chen","doi":"10.1145/2950067.2950096","DOIUrl":"https://doi.org/10.1145/2950067.2950096","url":null,"abstract":"As the first large-scale commercial spiking-based neuromorphic computing platform, IBM TrueNorth chip received tremendous attentions in society. However, one of the known issues in TrueNorth design is the limited precision of synaptic weights, each of which can be selected from only four integers. The current workaround is running multiple neural network copies of which the average value of each synaptic weight is close to that in the original network. To improve the computation accuracy and reduce the incurred hardware cost, in this work, we investigate seven different regularization functions in the cost function of the learning process on TrueNorth platform. The hypothesis is that the quantization loss in the mapping from the trained network in floating-point data format to TrueNorth chip with limited integer values shall be minimized if the discrepancy between the trained weight and the quantized weights by optimizing the training process. Our experimental results proved that the proposed techniques considerably improve the computation accuracy of TrueNorth platform and reduce the incurred hardware and performance overheads. Among all the tested methods, L1TEA regularization achieved the best result, say, up to 2.74% accuracy enhancement when deploying MNIST application onto TrueNorth platform.","PeriodicalId":213559,"journal":{"name":"2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132495012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Low power in-memory computing platform with four Terminal magnetic Domain Wall Motion devices 具有四个终端磁畴壁运动器件的低功耗内存计算平台

2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2016-07-18 DOI: 10.1145/2950067.2950084

Deliang Fan

{"title":"Low power in-memory computing platform with four Terminal magnetic Domain Wall Motion devices","authors":"Deliang Fan","doi":"10.1145/2950067.2950084","DOIUrl":"https://doi.org/10.1145/2950067.2950084","url":null,"abstract":"The separation of memory and computing units in current Von-Neumann computer architecture leads to unwanted energy hungry data movement and insufficient memory bandwidth. Developing an energy efficient in-memory computing platform is promising to address such issues. Spintronic devices, utilizing electron spin as state variable for information processing and data storage, have demonstrated non-volatility, low power, zero leakage current and high area density advantages over conventional CMOS technology, which makes it an excellent candidate for future in-memory computing design. In this work, we propose a low power in-memory computing platform using a novel 4-terminal magnetic domain wall motion (4T-DWM) device, in which the proposed 4T-DWM device can be employed as both non-volatile memory cell and in-memory logic. The proposed design leads to the unity of memory and logic. Based on our device-circuit SPICE-level simulation, the proposed memory cell writing energy is one order lower than the standard one transistor one magnetic tunnel junction (MTJ) based memory design with writing speed of 1ns. Compared to state-of-the-art CMOS based full adder, the proposed 4T-DWM device based in-memory full adder consumes 3.2× lower power at 500MHz.","PeriodicalId":213559,"journal":{"name":"2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125377377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Error Correction Code protected Data Processing Units 纠错码保护的数据处理单元

2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2016-07-18 DOI: 10.1145/2950067.2950093

N. C. Laurenciu, T. Gupta, V. Savin, S. Cotofana

{"title":"Error Correction Code protected Data Processing Units","authors":"N. C. Laurenciu, T. Gupta, V. Savin, S. Cotofana","doi":"10.1145/2950067.2950093","DOIUrl":"https://doi.org/10.1145/2950067.2950093","url":null,"abstract":"The significant uncertainty associated with current nanodevices fabrication and operation, calls for a circuit design paradigm change, which ought to actively embrace the inherently nanodevice unreliability to generate overall circuit architectures able to perform reliable computation. While for data storage units viable solutions exist, Data Processing Units (DPUs) are not amenable to a similar line of reasoning. The typical approach undertaken for fault-tolerant DPUs relies on modular redundancy (e.g., spatial, temporal), which while being effective from an error tolerance perspective, generally involves high area and/or performance impairments. This paper proposes a generic methodology to obtain reliable DPU implementations built with unreliable components by intimately intertwining Error Correcting Codes (ECCs) codecs with the DPU functionality. The ECC protected DPU architecture is derived cluster-wise with area and reliability constraints, by exploiting dependence relations (logical and w.r.t. shared area) between internal signals pertaining to the DPU and the ECC codec. To evaluate the error rate and performance implications, a multitude of test corners were considered (e.g., gate criticality, ECC type and structure, faulty and low complexity decoder, time-space redundancy) for an ECC protected 6-bit adder architecture. Simulation results reveal that the ECC embedding approach can be effective from both error rate and area perspective, for the Pareto designs with performance figures of merit situated in-between consecutive modular redundancy based design corresponding curves. The proposed approach is generic from the coding point of view, scalable, and enables a fine grained control of the DPU desired reliability degree and area overhead.","PeriodicalId":213559,"journal":{"name":"2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125224322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5