Sleep stage classification with stochastic Bayesian inference

Abstract

The design of electronic circuits that can realize Bayesian inference is an important goal for exploiting machine learning in a fast and efficient way. We recently developed a novel architecture based on stochastic computation with Muller C-elements that can realize a circuit level naïve Bayes inference. This technique can be implemented using low power nanodevices exhibiting faults and device variations. Here we show how a more complex classification problem can be transformed into a simple circuit using this framework where an effective classification can be obtained with a minimal amount of information. This suggests that substantially smaller spatial footprints for portable devices could ultimately be achieved.