2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)最新文献_第4页

Design of approximate Redundant Binary multipliers 近似冗余二进制乘法器的设计

2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2016-07-18 DOI: 10.1145/2950067.2950094

Tian Cao, Weiqiang Liu, Chenghua Wang, Xiaoping Cui, F. Lombardi

引用次数: 5

TFET NDR skewed inverter based sensing method 基于ttfet NDR偏斜逆变器的传感方法

2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2016-07-18 DOI: 10.1145/2950067.2950069

N. Gupta, A. Makosiej, A. Vladimirescu, A. Amara, S. Cotofana, C. Anghel

引用次数: 3

Towards automatic thermal network extraction in 3D ICs 三维集成电路中热网络的自动提取

2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2016-07-18 DOI: 10.1145/2950067.2950095

Mingyu Li, S. Khasanvis, Jiajun Shi, Sachin Bhat, Mostafizur Rahman, C. A. Moritz

{"title":"Towards automatic thermal network extraction in 3D ICs","authors":"Mingyu Li, S. Khasanvis, Jiajun Shi, Sachin Bhat, Mostafizur Rahman, C. A. Moritz","doi":"10.1145/2950067.2950095","DOIUrl":"https://doi.org/10.1145/2950067.2950095","url":null,"abstract":"Thermal management is one of the critical challenges in 3D integrated circuits. Incorporating thermal optimizations during the circuit design stages requires a convenient automatic method of doing thermal characterization for feedback purposes. In this paper, we present a methodology, which supports thermal characterization by automatically extracting the steady-state thermal modeling resistance network from a post-placement physical design. The method follows a two-level hierarchical approach. It does fine-grained thermal modeling for standard cells, and then at higher level assembles the thermal modeling network of the input physical design by using the built standard cell thermal models, and adding the information on inter-cell connections as well as implemented thermal management features. The methodology has been implemented in Skybridge-3D-CMOS technology, but can be employed in other fine-grained 3D directions such as monolithic 3D CMOS. Large scale benchmarking has been performed, showing the ability of doing automated fine-grained thermal characterization in the order of seconds per thousands of 3D standard cells. In addition, the methodology is employed to highlight implications of added thermal extraction features.","PeriodicalId":213559,"journal":{"name":"2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"204 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124576485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A fully parallel approximate CORDIC design 一个完全平行的近似CORDIC设计

2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2016-07-18 DOI: 10.1145/2950067.2950076

Linbin Chen, F. Lombardi, Jie Han, Weiqiang Liu

{"title":"A fully parallel approximate CORDIC design","authors":"Linbin Chen, F. Lombardi, Jie Han, Weiqiang Liu","doi":"10.1145/2950067.2950076","DOIUrl":"https://doi.org/10.1145/2950067.2950076","url":null,"abstract":"This paper proposes a new approximate scheme for a coordinate rotation digital computer (CORDIC) design; this scheme is based on modifying the existing Para-CORDIC architecture with multiple approximations. These approximations make possible a relaxation of the CORDIC algorithm itself, such that a fully parallel approximate CORDIC (FPAX-CORDIC) scheme is designed. This scheme avoids the memory register of Para-CORDIC and makes fully parallel the generation of the rotation direction. A comprehensive analysis and the evaluation of the error introduced by the approximations together with different circuit-related metrics are pursued using HSPICE as simulation tool. The error analysis of this paper combines existing figures of merit for approximate computing (such as the Mean Error Distance (MED)) with CORDIC-specific parameters; a good agreement between expected and simulated error values is found. As an application to image processing, the Discrete Cosine Transformation (DCT) is investigated by utilizing the proposed approximate FPAX-CORDIC architecture with different accuracy requirements. The results confirm the viability of the proposed scheme.","PeriodicalId":213559,"journal":{"name":"2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128962324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Ultra-low power all spin logic device acceleration based on voltage controlled magnetic anisotropy 基于压控磁各向异性的超低功耗全自旋逻辑器件加速

2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2016-07-01 DOI: 10.1145/2950067.2950103

Zhizhong Zhang, Yue Zhang, Lei Yue, Li Su, Yichuan Shi, Youguang Zhang, Weisheng Zhao

引用次数: 0

Approximate computing in MOS/spintronic non-volatile full-adder MOS/自旋电子非易失性全加法器的近似计算

2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2016-07-01 DOI: 10.1145/2950067.2950101

Hao Cai, You Wang, L. Naviner, Zhaohao Wang, Weisheng Zhao

引用次数: 16

Routability in 3D IC design: Monolithic 3D vs. Skybridge 3D CMOS 3D集成电路设计中的可达性:单片3D与Skybridge 3D CMOS

2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2016-04-29 DOI: 10.1145/2950067.2950078

Jiajun Shi, Mingyu Li, S. Khasanvis, Mostafizur Rahman, C. A. Moritz

{"title":"Routability in 3D IC design: Monolithic 3D vs. Skybridge 3D CMOS","authors":"Jiajun Shi, Mingyu Li, S. Khasanvis, Mostafizur Rahman, C. A. Moritz","doi":"10.1145/2950067.2950078","DOIUrl":"https://doi.org/10.1145/2950067.2950078","url":null,"abstract":"Conventional 2D CMOS technology is reaching fundamental scaling limits, and interconnect bottleneck is dominating integrated circuit (IC) power and performance. While 3D IC technologies using Through Silicon Via or Monolithic Inter-layer Via alleviate some of these challenges, they follow a similar layout and routing mindset as 2D CMOS. This is insufficient to address routing requirements in high-density 3D ICs and even causes severe routing congestion at large-scale designs, limiting their benefits and scalability. Skybridge is a recently proposed fine-grained 3D IC fabric relying on vertical nanowires that presents a paradigm shift for scaling, while addressing associated 3D connectivity and manufacturability challenges. Skybridge's core fabric components enable a new 3D IC design approach with vertically-composed logic gates, and provide a greater degree of routing flexibility compared to conventional 2D and 3D ICs leading to much larger benefits and future scalability. In this paper, we present a methodology using relevant metrics to evaluate and quantify the benefits of Skybridge vs. state-of-the-art transistor-level monolithic 3D IC (T-MI) and 2D in terms of routability and its impact on large-scale circuits. This is enabled by a new device-to-system design flow with commercial CAD tools that we developed for large-scale Skybridge IC designs in 16nm node. Evaluation for standard benchmark circuits shows that Skybridge yields up to 1.6× lower routing demand against T-MI with no routing congestion (routing demand to resource ratio <; 1) at all metal layers. This 3D routability in conjunction with compact vertical gate design in Skybridge translate into benefits of up to 3× lower power and 11× higher density over 2D CMOS, while TLM-3DIC approach only has up to 22% power saving and 2× density improvement over 2D CMOS.","PeriodicalId":213559,"journal":{"name":"2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"21 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132747829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9