Proceedings VHDL International Users' Forum. Fall Conference最新文献_第3页

Redesign of a generic VHDL model template for SRAMs sram通用VHDL模型模板的重新设计

Proceedings VHDL International Users' Forum. Fall Conference Pub Date : 1997-10-19 DOI: 10.1109/VIUF.1997.623940

C. McCloskey, R. Reese, V. Sanders

引用次数: 2

IEEE VHDL 1076.1: mixed-signal behavioral modeling and verification in view of automotive applications IEEE VHDL 1076.1:鉴于汽车应用的混合信号行为建模和验证

Proceedings VHDL International Users' Forum. Fall Conference Pub Date : 1997-10-19 DOI: 10.1109/VIUF.1997.623957

J. Papanuskas

引用次数: 5

Processes with 'incomplete' sensitivity lists and their synthesis aspects 具有“不完全”敏感性表的工艺及其合成方面

Proceedings VHDL International Users' Forum. Fall Conference Pub Date : 1997-10-19 DOI: 10.1109/VIUF.1997.623933

Egbert Molenkamp, G. Mekenkamp

{"title":"Processes with 'incomplete' sensitivity lists and their synthesis aspects","authors":"Egbert Molenkamp, G. Mekenkamp","doi":"10.1109/VIUF.1997.623933","DOIUrl":"https://doi.org/10.1109/VIUF.1997.623933","url":null,"abstract":"Synthesis tools only support a subset of VHDL. In this paper, we focus on the synthesis aspects of processes with an incomplete sensitivity list. In general, processes with a sensitivity list are used to describe combinational logic and clocked logic. The sensitivity list is called 'complete' when all signals which are read from within that process are in the sensitivity list, otherwise it has an 'incomplete' sensitivity list. Most, if not all, synthesis tools require that the processes used to describe combinational logic should have a 'complete' sensitivity list, while for synchronous logic only the reset, if any, and clock signals should be in the sensitivity list. Beside these two applications of processes with sensitivity lists, there is a vague support for other incomplete sensitivity lists, sometimes resulting in latches in the circuit and sometimes resulting in logic that does not have the proper behaviour. This paper focuses on the synthesis aspects of processes with an incomplete sensitivity list, and presents a method to synthesise a subset of these processes. Also, the problem of synthesising processes with an incomplete sensitivity list is discussed.","PeriodicalId":212876,"journal":{"name":"Proceedings VHDL International Users' Forum. Fall Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129045893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Proposing graphic extensions to VHDL 提出图形扩展到VHDL

Proceedings VHDL International Users' Forum. Fall Conference Pub Date : 1997-10-19 DOI: 10.1109/VIUF.1997.623938

T. Hadlich

{"title":"Proposing graphic extensions to VHDL","authors":"T. Hadlich","doi":"10.1109/VIUF.1997.623938","DOIUrl":"https://doi.org/10.1109/VIUF.1997.623938","url":null,"abstract":"VHDL is a text-based hardware description language but, traditionally, graphical representation was used for describing the structure and the architecture of hardware. Even today, the leading tools offer some graphical design entry and thus a graphical representation of its models. In general, these representations are not compatible to each other and, when transferring the VHDL model from one toolset to another, the graphical representation is lost. Also, when introducing an audience to a new hardware concept, the graphical representation helps for an easy understanding of the presented concepts. A solution to this situation would be to define a standard graphical representation for VHDL constructs. The graphical representation could be restricted to a standard representation of structural constructs. The graphical representation of behavioral constructs could be made open to the tool vendors. This definition does not require a change of VHDL in itself. A similar approach was taken to the formal description languages SDL and MSC, which have, besides their textual representation, a graphical representation. The author has had good experiences with SDL, which is a formal description technique. The language is powerful, has a growing acceptance and is well suited for hardware/software codesign. Based on this experience, the proposal for a graphical representation of VHDL is presented in this paper. The paper starts with a short introduction to SDL, followed by a demonstration of how graphic constructs could increase the acceptance of VHDL.","PeriodicalId":212876,"journal":{"name":"Proceedings VHDL International Users' Forum. Fall Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116218679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Extending VHDL to the systems level 将VHDL扩展到系统级

Proceedings VHDL International Users' Forum. Fall Conference Pub Date : 1997-10-19 DOI: 10.1109/VIUF.1997.623936

Perry Alexander, P. Baraona

引用次数: 2

Fast prototyping of an ASIC for ATM application using a synthesizable VHDL flexible library 使用可合成的VHDL灵活库的ATM应用的ASIC快速原型

Proceedings VHDL International Users' Forum. Fall Conference Pub Date : 1997-10-19 DOI: 10.1109/VIUF.1997.623935

S. Claretto, E. Filippi, A. Montanaro, M. Paolini, M. Turolla

引用次数: 2

VHDL modeling and tutoring efforts by Mississippi State University VHDL建模和辅导工作密西西比州立大学

Proceedings VHDL International Users' Forum. Fall Conference Pub Date : 1997-10-19 DOI: 10.1109/VIUF.1997.623948

R. Reese, D. T. Brown

引用次数: 0

VHDL design environment for legacy electronics (VDELE) 用于传统电子产品的VHDL设计环境(VDELE)

Proceedings VHDL International Users' Forum. Fall Conference Pub Date : 1997-10-19 DOI: 10.1109/VIUF.1997.623946

J.A. Houston, L. Concha, R. Bohannan

{"title":"VHDL design environment for legacy electronics (VDELE)","authors":"J.A. Houston, L. Concha, R. Bohannan","doi":"10.1109/VIUF.1997.623946","DOIUrl":"https://doi.org/10.1109/VIUF.1997.623946","url":null,"abstract":"The rapidly escalating DMS (Diminishing Manufacturing Sources) problem for digital electronic components is seriously impacting the ability of avionics equipment suppliers to provide affordable equipment to new aircraft. Sustainment of this equipment in the field is a major cost driver in the O&S (Operation & Support) cost equation due to the same problem. The development of F/sup 3/I (Form-Fit-Function-Interface) printed circuit assembly (PCA) level replacements for obsolete digital electronics provides the opportunity to solve both of these problems at minimum cost. The Wright Laboratories sponsored VDELE (VHDL Design Environment for Legacy Electronics) project has developed innovative methodologies for the development of F/sup 3/I clones for PCAs that have become obsolete due to DMS problems. The VDELE process extracts VHDL model and test information from the customer digital database and then applies commercially available tools to refine and validate the model in a virtual development environment. The refined VHDL simulation model is then provided to a qualified supplier in the form of a technology independent executable specification for synthesis into a clone PCA replacement. We present a brief description of the VDELE process and the application of the VDELE methodologies to the development of an FPGA (field programmable gate array) based prototype for an F-16 PCA seriously impacted by the DMS problem.","PeriodicalId":212876,"journal":{"name":"Proceedings VHDL International Users' Forum. Fall Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128317926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A hybrid event-simulation/cycle-simulation environment for VHDL-based designs 基于vhdl设计的混合事件模拟/循环模拟环境

Proceedings VHDL International Users' Forum. Fall Conference Pub Date : 1997-10-19 DOI: 10.1109/VIUF.1997.623958

M. Cogswell, D. Wood

引用次数: 2

Hardware/software co-design in the rapid prototyping of application-specific signal processors methodology 硬件/软件协同设计的快速原型应用特定的信号处理器方法

Proceedings VHDL International Users' Forum. Fall Conference Pub Date : 1997-10-19 DOI: 10.1109/VIUF.1997.623956

W. Schaming

引用次数: 0