A hybrid event-simulation/cycle-simulation environment for VHDL-based designs

Abstract

The need for flexible high-level simulation environments continues to persist due to increasingly high-density chip technologies coupled with ever-decreasing product cycle times. The simulation development team at IBM-Rochester has designed a durable simulation environment providing a highly abstract test-case language and an adaptable model interface. The environment consists of three types of models: the hardware being verified (concurrent VHDL), behavior models (sequential VHDL) and the simulation control manager (sequential VHDL). Initially, the entire environment was run on an event-simulation engine, but capacity limitations obviated the need to consider use of cycle simulation. However, the cycle-simulation engine in use at Rochester had no inherent support for sequential VHDL. The resulting solution required the development of a hybrid simulation environment which combined the best of both types of simulation engines. The architecture, implementation, benefits and limitations of this hybrid environment are the subject of this paper.