{"title":"基于vhdl设计的混合事件模拟/循环模拟环境","authors":"M. Cogswell, D. Wood","doi":"10.1109/VIUF.1997.623958","DOIUrl":null,"url":null,"abstract":"The need for flexible high-level simulation environments continues to persist due to increasingly high-density chip technologies coupled with ever-decreasing product cycle times. The simulation development team at IBM-Rochester has designed a durable simulation environment providing a highly abstract test-case language and an adaptable model interface. The environment consists of three types of models: the hardware being verified (concurrent VHDL), behavior models (sequential VHDL) and the simulation control manager (sequential VHDL). Initially, the entire environment was run on an event-simulation engine, but capacity limitations obviated the need to consider use of cycle simulation. However, the cycle-simulation engine in use at Rochester had no inherent support for sequential VHDL. The resulting solution required the development of a hybrid simulation environment which combined the best of both types of simulation engines. The architecture, implementation, benefits and limitations of this hybrid environment are the subject of this paper.","PeriodicalId":212876,"journal":{"name":"Proceedings VHDL International Users' Forum. Fall Conference","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1997-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A hybrid event-simulation/cycle-simulation environment for VHDL-based designs\",\"authors\":\"M. Cogswell, D. Wood\",\"doi\":\"10.1109/VIUF.1997.623958\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The need for flexible high-level simulation environments continues to persist due to increasingly high-density chip technologies coupled with ever-decreasing product cycle times. The simulation development team at IBM-Rochester has designed a durable simulation environment providing a highly abstract test-case language and an adaptable model interface. The environment consists of three types of models: the hardware being verified (concurrent VHDL), behavior models (sequential VHDL) and the simulation control manager (sequential VHDL). Initially, the entire environment was run on an event-simulation engine, but capacity limitations obviated the need to consider use of cycle simulation. However, the cycle-simulation engine in use at Rochester had no inherent support for sequential VHDL. The resulting solution required the development of a hybrid simulation environment which combined the best of both types of simulation engines. The architecture, implementation, benefits and limitations of this hybrid environment are the subject of this paper.\",\"PeriodicalId\":212876,\"journal\":{\"name\":\"Proceedings VHDL International Users' Forum. Fall Conference\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-10-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings VHDL International Users' Forum. Fall Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VIUF.1997.623958\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings VHDL International Users' Forum. Fall Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VIUF.1997.623958","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A hybrid event-simulation/cycle-simulation environment for VHDL-based designs
The need for flexible high-level simulation environments continues to persist due to increasingly high-density chip technologies coupled with ever-decreasing product cycle times. The simulation development team at IBM-Rochester has designed a durable simulation environment providing a highly abstract test-case language and an adaptable model interface. The environment consists of three types of models: the hardware being verified (concurrent VHDL), behavior models (sequential VHDL) and the simulation control manager (sequential VHDL). Initially, the entire environment was run on an event-simulation engine, but capacity limitations obviated the need to consider use of cycle simulation. However, the cycle-simulation engine in use at Rochester had no inherent support for sequential VHDL. The resulting solution required the development of a hybrid simulation environment which combined the best of both types of simulation engines. The architecture, implementation, benefits and limitations of this hybrid environment are the subject of this paper.