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Proceedings VHDL International Users' Forum. Fall Conference最新文献

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A performance modeling framework applied to real time infrared search and track processing 一种用于红外实时搜索与跟踪处理的性能建模框架
Proceedings VHDL International Users' Forum. Fall Conference Pub Date : 1997-10-19 DOI: 10.1109/VIUF.1997.623927
E. Pauer, M. Pettigrew, C. S. Myers, V. Madisetti
{"title":"A performance modeling framework applied to real time infrared search and track processing","authors":"E. Pauer, M. Pettigrew, C. S. Myers, V. Madisetti","doi":"10.1109/VIUF.1997.623927","DOIUrl":"https://doi.org/10.1109/VIUF.1997.623927","url":null,"abstract":"The purpose and goals of performance modeling for multiprocessor systems using a token-based methodology in VHDL are discussed. Following this motivation, a framework for performance modeling is described, which involves modeling hardware and software at different levels of abstraction; the scope of the paper primarily addresses the high profile performance model. A commercial tool supporting this modeling framework is then introduced. The discussion continues with an overview of the real time infrared search and track algorithm, and the system design problem. Preliminary results of the performance modeling efforts and validation via code profiling is summarized, and future plans are described.","PeriodicalId":212876,"journal":{"name":"Proceedings VHDL International Users' Forum. Fall Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122948273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Supporting hardware trade analysis and cost estimation using design complexity 支持硬件交易分析和使用设计复杂性的成本估算
Proceedings VHDL International Users' Forum. Fall Conference Pub Date : 1997-10-19 DOI: 10.1109/VIUF.1997.623941
P.W. Salchak, P. Chawla
{"title":"Supporting hardware trade analysis and cost estimation using design complexity","authors":"P.W. Salchak, P. Chawla","doi":"10.1109/VIUF.1997.623941","DOIUrl":"https://doi.org/10.1109/VIUF.1997.623941","url":null,"abstract":"Defines and illustrates a hardware design complexity measure (HDCM) and describe its potential applications to trade-off analysis and cost estimation. Specifically, we define a VHDL complexity measure. We have derived the HDCM from an avionics software design complexity measure (ASDCM) that we have shown to be effective in estimation and optimization of overall software costs. Similar to the ASDCM, we believe that the proposed HDCM could enable more optimal hardware design, implementation and maintenance.","PeriodicalId":212876,"journal":{"name":"Proceedings VHDL International Users' Forum. Fall Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121123778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
RTL based scan BIST 基于RTL的扫描
Proceedings VHDL International Users' Forum. Fall Conference Pub Date : 1997-10-19 DOI: 10.1109/VIUF.1997.623939
R. Subrata
{"title":"RTL based scan BIST","authors":"R. Subrata","doi":"10.1109/VIUF.1997.623939","DOIUrl":"https://doi.org/10.1109/VIUF.1997.623939","url":null,"abstract":"The synthesis of ASICs from register transfer level (RTL) sources is often a bottom-up iterative process where the synthesis process is carefully controlled to produce a gate-level design which meets the desired constraints. Test logic, such as built-in self-test (BIST), is typically inserted at the gate level. This may cause new violations of timing/area goals, thus causing an expensive cycle of re-optimization on the complete chip at the end of the design process. Performing BIST logic insertion at the RTL source allows synthesis technology to consider test logic while optimizing to meet area/timing goals, thus avoiding an expensive re-optimization. It also provides an opportunity for the sharing of functional and test logic. Scan-based BIST utilizes scan chains to apply random vectors and to observe signal values within the random logic. This paper describes techniques for inserting scan chains at the RTL-VHDL source in the context of scan BIST, and reports its impact on design optimization and fault coverage.","PeriodicalId":212876,"journal":{"name":"Proceedings VHDL International Users' Forum. Fall Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127870540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Hardware/software codesign of a scalable embedded radar signal processor 可扩展嵌入式雷达信号处理器的硬件/软件协同设计
Proceedings VHDL International Users' Forum. Fall Conference Pub Date : 1997-10-19 DOI: 10.1109/VIUF.1997.623951
Charles W. Buenzli, L. Owen, F. Rose
{"title":"Hardware/software codesign of a scalable embedded radar signal processor","authors":"Charles W. Buenzli, L. Owen, F. Rose","doi":"10.1109/VIUF.1997.623951","DOIUrl":"https://doi.org/10.1109/VIUF.1997.623951","url":null,"abstract":"The RASSP performance modeling methodology was used to rapidly model and compare alternative hardware/software architectures for a scalable embedded radar signal processor based on COTS DSP boards. VHDL performance models were generated from graphical hardware and software architectures using Cosmos/sup TM/, simulated with QuickHDL/sup TM/, and analyzed with Cosmos. Results for a Mercury RACEway/sup TM/ architecture are presented.","PeriodicalId":212876,"journal":{"name":"Proceedings VHDL International Users' Forum. Fall Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132078382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Component modeling for reliability analysis by simulation 通过仿真进行可靠性分析的构件建模
Proceedings VHDL International Users' Forum. Fall Conference Pub Date : 1997-10-19 DOI: 10.1109/VIUF.1997.623954
B. Alizadeh, Z. Navabi
{"title":"Component modeling for reliability analysis by simulation","authors":"B. Alizadeh, Z. Navabi","doi":"10.1109/VIUF.1997.623954","DOIUrl":"https://doi.org/10.1109/VIUF.1997.623954","url":null,"abstract":"This paper presents a method of reliability analysis by simulation. Hardware level modularity in creating a simulation model is achieved by use of the VHDL language. Each hardware component is individually modeled in VHDL for calculation of its failure time based on its reliability. VHDL simulation results are compared for common structures with known reliability analysis methods such as Markov model.","PeriodicalId":212876,"journal":{"name":"Proceedings VHDL International Users' Forum. Fall Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114599920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
VHDL models supporting a system-level design process: a RASSP approach 支持系统级设计过程的VHDL模型:RASSP方法
Proceedings VHDL International Users' Forum. Fall Conference Pub Date : 1997-10-19 DOI: 10.1109/VIUF.1997.623949
J. Debardelaben, V. Madisetti, A. Gadient
{"title":"VHDL models supporting a system-level design process: a RASSP approach","authors":"J. Debardelaben, V. Madisetti, A. Gadient","doi":"10.1109/VIUF.1997.623949","DOIUrl":"https://doi.org/10.1109/VIUF.1997.623949","url":null,"abstract":"The successful Rapid Prototyping of Application-Specific Signal Processors (RASSP) program of the US Department of Defense (DARPA and Tri-Services) targets a 4/spl times/ improvement in cost and cycle time for design, prototyping, manufacturing, and support processes (relative to current practice). We describe a RASSP-based virtual prototyping process which incorporates parametric cost modeling into a hardware-less VHDL co-simulation and co-verification environment for rapid prototyping. We demonstrate this VHDL-based approach by applying it to the design of a synthetic aperture radar (SAR) system. We present quantitative estimates of the improvements in prototyping time and cost.","PeriodicalId":212876,"journal":{"name":"Proceedings VHDL International Users' Forum. Fall Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132072755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
SCUBA: an HDL data-path/memory module generator for FPGAs 用于fpga的HDL数据路径/内存模块生成器
Proceedings VHDL International Users' Forum. Fall Conference Pub Date : 1997-10-19 DOI: 10.1109/VIUF.1997.623942
S. Mohanty, K. Maheswaran, S. Haruyama, Jiang Niu
{"title":"SCUBA: an HDL data-path/memory module generator for FPGAs","authors":"S. Mohanty, K. Maheswaran, S. Haruyama, Jiang Niu","doi":"10.1109/VIUF.1997.623942","DOIUrl":"https://doi.org/10.1109/VIUF.1997.623942","url":null,"abstract":"Lucent Technologies' ORCA (Optimized Reconfigurable Cell Array) FPGAs, with their nibble-oriented architecture, are especially suitable for data-path-intensive circuits. The current design flows do not fully utilize the data-path and memory capabilities in the ORCA architecture. To fully utilize the capability of ORCA's flexible data-path blocks and to provide the designer with the flexibility of accessing the architectural features of ORCA, the tool SCUBA (Synthesis Compiler for User-programmaBle Arrays) was developed and integrated into the ORCA design flow. SCUBA synthesizes parametrized data-path and memory blocks in VHDL/Verilog/EDIF, which are optimized for the ORCA architecture. SCUBA can also provide optimal positional information to a placer. By preserving regularity information of a circuit network structure in a layout tool, the performance of the synthesized circuits improves substantially. SCUBA also provides a means for exploring future-generation architectures by providing interface blocks for designing complex structures, such as application-specific blocks.","PeriodicalId":212876,"journal":{"name":"Proceedings VHDL International Users' Forum. Fall Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113945901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
VHDL-based performance modeling: an application of the PMW tool suite to an image classification system 基于vhdl的性能建模:PMW工具套件在图像分类系统中的应用
Proceedings VHDL International Users' Forum. Fall Conference Pub Date : 1997-10-19 DOI: 10.1109/VIUF.1997.623952
J. Ammon, C. Hein
{"title":"VHDL-based performance modeling: an application of the PMW tool suite to an image classification system","authors":"J. Ammon, C. Hein","doi":"10.1109/VIUF.1997.623952","DOIUrl":"https://doi.org/10.1109/VIUF.1997.623952","url":null,"abstract":"In a simulation-based design process developed for the Rapid Prototyping of Application-Specific Signal Processors program (RASSP), an abstract VHDL performance model forms a virtual prototype of a full DSP system that is timing- and data-faithful. Full-system models provide early design verification by simulating application software and hardware in an integrated co-design development. This paper describes the process of applying Omniview's PMW tool suite to the design of an image-classification system. The Performance Modeling Workbench (PMW) tool suite lets engineers create high-fidelity performance models of multiprocessor systems. The design process uses performance models for trade-off analyses among designs with different hardware/software architectures. The tool helps designers determine if the candidate design could satisfy performance requirements, identify bottlenecks and over-design, and optimize system performance.","PeriodicalId":212876,"journal":{"name":"Proceedings VHDL International Users' Forum. Fall Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133853945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A symbol based algorithm for hardware implementation of cyclic redundancy check (CRC) 基于符号的循环冗余校验(CRC)硬件实现算法
Proceedings VHDL International Users' Forum. Fall Conference Pub Date : 1997-10-19 DOI: 10.1109/VIUF.1997.623934
R. Nair, G. Ryan, F. Farzaneh
{"title":"A symbol based algorithm for hardware implementation of cyclic redundancy check (CRC)","authors":"R. Nair, G. Ryan, F. Farzaneh","doi":"10.1109/VIUF.1997.623934","DOIUrl":"https://doi.org/10.1109/VIUF.1997.623934","url":null,"abstract":"Describes a symbolic simulation-based algorithm to derive optimized Boolean equations for a parameterizable data width CRC generator/checker. The equations are then used to implement a data flow representation of the CRC circuit in VHDL. The VHDL description is subsequently synthesized to gates. The area and timing results of the hardware implementation are presented and compared with a conventional loop iteration technique (also described in this paper). The CRC-32 polynomial, commonly used for most computer network protocol standards, was chosen to implement the algorithm.","PeriodicalId":212876,"journal":{"name":"Proceedings VHDL International Users' Forum. Fall Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123940749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
A new methodology and generic model library for the rapid prototyping of real-time image processing systems 一种用于实时图像处理系统快速原型设计的新方法和通用模型库
Proceedings VHDL International Users' Forum. Fall Conference Pub Date : 1997-10-19 DOI: 10.1109/VIUF.1997.623960
D. Gibson, M. Teal, D. Ait-Boudaoud, M. Winchester
{"title":"A new methodology and generic model library for the rapid prototyping of real-time image processing systems","authors":"D. Gibson, M. Teal, D. Ait-Boudaoud, M. Winchester","doi":"10.1109/VIUF.1997.623960","DOIUrl":"https://doi.org/10.1109/VIUF.1997.623960","url":null,"abstract":"The foremost objective of system designers is to develop hardware with the correct functionality in the shortest possible time. Therefore, they are keen to exploit any methodology that will help to reduce development times, increase reuse and make 'right first time' design an achievable target. This paper proposes a method that permits rapid prototyping of custom hardware for the implementation of real-time image processing systems. This methodology consists of partitioning the system into component blocks and then prototyping using a library of generic VHDL models. Each component model has a standard interface and has been simulated and synthesised to a technology-independent level. Systems can be quickly and easily constructed using this library and a model-oriented design flow. This technique permits the rapid prototyping of hardware whilst allowing the functionality and performance of the proposed system to be quickly assessed and verified throughout the design cycle.","PeriodicalId":212876,"journal":{"name":"Proceedings VHDL International Users' Forum. Fall Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129075584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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