{"title":"支持系统级设计过程的VHDL模型:RASSP方法","authors":"J. Debardelaben, V. Madisetti, A. Gadient","doi":"10.1109/VIUF.1997.623949","DOIUrl":null,"url":null,"abstract":"The successful Rapid Prototyping of Application-Specific Signal Processors (RASSP) program of the US Department of Defense (DARPA and Tri-Services) targets a 4/spl times/ improvement in cost and cycle time for design, prototyping, manufacturing, and support processes (relative to current practice). We describe a RASSP-based virtual prototyping process which incorporates parametric cost modeling into a hardware-less VHDL co-simulation and co-verification environment for rapid prototyping. We demonstrate this VHDL-based approach by applying it to the design of a synthetic aperture radar (SAR) system. We present quantitative estimates of the improvements in prototyping time and cost.","PeriodicalId":212876,"journal":{"name":"Proceedings VHDL International Users' Forum. Fall Conference","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1997-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"VHDL models supporting a system-level design process: a RASSP approach\",\"authors\":\"J. Debardelaben, V. Madisetti, A. Gadient\",\"doi\":\"10.1109/VIUF.1997.623949\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The successful Rapid Prototyping of Application-Specific Signal Processors (RASSP) program of the US Department of Defense (DARPA and Tri-Services) targets a 4/spl times/ improvement in cost and cycle time for design, prototyping, manufacturing, and support processes (relative to current practice). We describe a RASSP-based virtual prototyping process which incorporates parametric cost modeling into a hardware-less VHDL co-simulation and co-verification environment for rapid prototyping. We demonstrate this VHDL-based approach by applying it to the design of a synthetic aperture radar (SAR) system. We present quantitative estimates of the improvements in prototyping time and cost.\",\"PeriodicalId\":212876,\"journal\":{\"name\":\"Proceedings VHDL International Users' Forum. Fall Conference\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-10-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings VHDL International Users' Forum. Fall Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VIUF.1997.623949\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings VHDL International Users' Forum. Fall Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VIUF.1997.623949","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
VHDL models supporting a system-level design process: a RASSP approach
The successful Rapid Prototyping of Application-Specific Signal Processors (RASSP) program of the US Department of Defense (DARPA and Tri-Services) targets a 4/spl times/ improvement in cost and cycle time for design, prototyping, manufacturing, and support processes (relative to current practice). We describe a RASSP-based virtual prototyping process which incorporates parametric cost modeling into a hardware-less VHDL co-simulation and co-verification environment for rapid prototyping. We demonstrate this VHDL-based approach by applying it to the design of a synthetic aperture radar (SAR) system. We present quantitative estimates of the improvements in prototyping time and cost.