RTL based scan BIST

Abstract

The synthesis of ASICs from register transfer level (RTL) sources is often a bottom-up iterative process where the synthesis process is carefully controlled to produce a gate-level design which meets the desired constraints. Test logic, such as built-in self-test (BIST), is typically inserted at the gate level. This may cause new violations of timing/area goals, thus causing an expensive cycle of re-optimization on the complete chip at the end of the design process. Performing BIST logic insertion at the RTL source allows synthesis technology to consider test logic while optimizing to meet area/timing goals, thus avoiding an expensive re-optimization. It also provides an opportunity for the sharing of functional and test logic. Scan-based BIST utilizes scan chains to apply random vectors and to observe signal values within the random logic. This paper describes techniques for inserting scan chains at the RTL-VHDL source in the context of scan BIST, and reports its impact on design optimization and fault coverage.