Component modeling for reliability analysis by simulation

B. Alizadeh, Z. Navabi
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引用次数: 1

Abstract

This paper presents a method of reliability analysis by simulation. Hardware level modularity in creating a simulation model is achieved by use of the VHDL language. Each hardware component is individually modeled in VHDL for calculation of its failure time based on its reliability. VHDL simulation results are compared for common structures with known reliability analysis methods such as Markov model.
通过仿真进行可靠性分析的构件建模
本文提出了一种基于仿真的可靠性分析方法。利用VHDL语言实现了仿真模型的硬件级模块化。每个硬件部件在VHDL中单独建模,根据其可靠性计算其故障时间。用已知的马尔可夫模型等可靠性分析方法对常见结构的VHDL仿真结果进行了比较。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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