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Proceedings VHDL International Users' Forum. Fall Conference最新文献

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On comparing different modeling styles [VHDL] 不同建模风格的比较[VHDL]
Proceedings VHDL International Users' Forum. Fall Conference Pub Date : 1997-10-19 DOI: 10.1109/VIUF.1997.623959
W. Ecker, J. Bottger, C. Ruschmeyer
{"title":"On comparing different modeling styles [VHDL]","authors":"W. Ecker, J. Bottger, C. Ruschmeyer","doi":"10.1109/VIUF.1997.623959","DOIUrl":"https://doi.org/10.1109/VIUF.1997.623959","url":null,"abstract":"VHDL plays a dominating role in today's system designs. Its primary application domain is currently focussed on RTL descriptions. One approach in dealing with the still dramatically increasing complexity of digital systems is to use VHDL more and more for executable specifications and complex test-benches. In this paper, we present the comparison results of models describing the same design unit using a set of different modeling styles in the domains of value representation, time representation and description style. We did not exclusively use VHDL, but took Ada programs into consideration describing the same unit using the same level of abstraction.","PeriodicalId":212876,"journal":{"name":"Proceedings VHDL International Users' Forum. Fall Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116906246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
OOVHDL: object oriented VHDL 面向对象的VHDL
Proceedings VHDL International Users' Forum. Fall Conference Pub Date : 1997-10-19 DOI: 10.1109/VIUF.1997.623929
Bachir Djafri, Judith Benzakki
{"title":"OOVHDL: object oriented VHDL","authors":"Bachir Djafri, Judith Benzakki","doi":"10.1109/VIUF.1997.623929","DOIUrl":"https://doi.org/10.1109/VIUF.1997.623929","url":null,"abstract":"In the last decade, VHDL has played an important role in the explosive growth of the electronic design automation industry and, currently, it is widely used by hardware systems designers in many projects. However to keep up with the steady increase in complexity of hardware systems, to allow reuse of design models, and to reduce development time and cost, new design methods must be found. Several documents and publications have proposed to extend VHDL and add object oriented features both to manage the complexity increase and to augment the capabilities and expressiveness of VHDL. The authors describe OOVHDL, which extends VHDL by adding object oriented features such as inheritance, polymorphism mechanism, and communication via messages. The object oriented extensions and the different constructs described in the paper are illustrated through some examples.","PeriodicalId":212876,"journal":{"name":"Proceedings VHDL International Users' Forum. Fall Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128993036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Reuse through genericity in SUAVE 在SUAVE中通过泛型重用
Proceedings VHDL International Users' Forum. Fall Conference Pub Date : 1997-10-19 DOI: 10.1109/VIUF.1997.623947
P. Ashenden, P. Wilsey, D.E. Martin
{"title":"Reuse through genericity in SUAVE","authors":"P. Ashenden, P. Wilsey, D.E. Martin","doi":"10.1109/VIUF.1997.623947","DOIUrl":"https://doi.org/10.1109/VIUF.1997.623947","url":null,"abstract":"VHDL currently has a limited form of genericity in which component and entity declarations can be parameterized with formal generic constants. SUAVE extends the genericity mechanism by allowing formal generics types and by allowing generics to be specified in the interfaces of subprograms and packages. The approach is based on the features of Ada-95. It allows units to be re-used in a much wider variety of contexts without modifying the original code. We show that the genericity added by SUAVE enhances reuse across the spectrum of modeling, from high-level to gate level. In particular, the genericity extensions interact with the SUAVE extensions for object-oriented data modeling to significantly improve support for high-level behavioral modeling and for developing test-benches. We show that the genericity extensions integrate seamlessly with the existing language. Furthermore, the implementation burden is not large, and since generic instantiation is performed at elaboration time, there is no performance penalty in simulation or synthesis.","PeriodicalId":212876,"journal":{"name":"Proceedings VHDL International Users' Forum. Fall Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129165325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Rapid-prototyping of high-performance RISC cores with VHDL 高性能RISC内核的VHDL快速原型设计
Proceedings VHDL International Users' Forum. Fall Conference Pub Date : 1997-10-19 DOI: 10.1109/VIUF.1997.623928
T. Bautista, G. Marrero, P. P. Carballo, A. Núñez
{"title":"Rapid-prototyping of high-performance RISC cores with VHDL","authors":"T. Bautista, G. Marrero, P. P. Carballo, A. Núñez","doi":"10.1109/VIUF.1997.623928","DOIUrl":"https://doi.org/10.1109/VIUF.1997.623928","url":null,"abstract":"The authors present some experiences they have obtained in the conception and description of a SPARC v8 IU core to be embedded in custom applications. Its design has been carried out using VHDL-based tools such as Synopsys for debugging and synthesis, and Cascade's Epoch for the final implementation stage. These experiences have been gathered into a proposed methodology for the rapid design of high-performance embeddable cores.","PeriodicalId":212876,"journal":{"name":"Proceedings VHDL International Users' Forum. Fall Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122799093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Implementing a complete test tool set in VHDL 在VHDL中实现一个完整的测试工具集
Proceedings VHDL International Users' Forum. Fall Conference Pub Date : 1997-10-19 DOI: 10.1109/VIUF.1997.623923
A. Peymandoust, Z. Navabi
{"title":"Implementing a complete test tool set in VHDL","authors":"A. Peymandoust, Z. Navabi","doi":"10.1109/VIUF.1997.623923","DOIUrl":"https://doi.org/10.1109/VIUF.1997.623923","url":null,"abstract":"As a concurrent programming environment, VHDL can be used for the implementation of most digital system test algorithms for test generation and fault simulation. The benefits are in easier implementations, due to the concurrent nature of VHDL, and a uniform hardware netlist format for all design and test applications. In this paper, the general methodologies for using VHDL in testing are presented and a specific example for adaptive random test generation is explained in detail.","PeriodicalId":212876,"journal":{"name":"Proceedings VHDL International Users' Forum. Fall Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114012169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Mixed-level modeling in VHDL using the watch-and-react interface 使用观察-反应接口的VHDL混合级建模
Proceedings VHDL International Users' Forum. Fall Conference Pub Date : 1997-10-19 DOI: 10.1109/VIUF.1997.623926
W. W. Dungan, R. Klenke, J. Aylor
{"title":"Mixed-level modeling in VHDL using the watch-and-react interface","authors":"W. W. Dungan, R. Klenke, J. Aylor","doi":"10.1109/VIUF.1997.623926","DOIUrl":"https://doi.org/10.1109/VIUF.1997.623926","url":null,"abstract":"Using VHDL, it is possible to model systems at many different levels of detail. The various modeling levels (performance, behavioral, etc.) can also be intermixed to create mixed-level models. The paper describes the watch-and-react interface which was created to resolve the differences in timing and data abstraction between the performance modeling domain (token based) and the behavioral modeling domain (value based). Specifically this interface is useful for integrating behavioral models of complex sequential components into performance models. It operates by monitoring the \"important\" signals in a system and then reacting to changes in these signals by generating tokens or forcing signals to appropriate values given the particular situation. The two main elements in the interface are the trigger and the driver. Program files containing scripting instructions are interpreted by the these two elements as the VHDL model simulates.","PeriodicalId":212876,"journal":{"name":"Proceedings VHDL International Users' Forum. Fall Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129742388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Reducing FPGA design modification time 减少FPGA设计修改时间
Proceedings VHDL International Users' Forum. Fall Conference Pub Date : 1997-10-19 DOI: 10.1109/VIUF.1997.623943
M. Lehky, S. Bilik
{"title":"Reducing FPGA design modification time","authors":"M. Lehky, S. Bilik","doi":"10.1109/VIUF.1997.623943","DOIUrl":"https://doi.org/10.1109/VIUF.1997.623943","url":null,"abstract":"An incremental approach to logic synthesis developed under the RASSP program is described. The approach reduces the time it takes to implement changes in an FPGA design. It also helps designers stay connected with the implementation issues and helps new synthesis users get over the learning curve. It involves resynthesizing only the blocks of the design that change, rather than the whole design. Existing blocks of unmodified logic are reused through the netlist merge capabilities of many foundry tools. Results show that the incremental approach helps speed up the total design cycle time.","PeriodicalId":212876,"journal":{"name":"Proceedings VHDL International Users' Forum. Fall Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124172824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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