{"title":"在VHDL中实现一个完整的测试工具集","authors":"A. Peymandoust, Z. Navabi","doi":"10.1109/VIUF.1997.623923","DOIUrl":null,"url":null,"abstract":"As a concurrent programming environment, VHDL can be used for the implementation of most digital system test algorithms for test generation and fault simulation. The benefits are in easier implementations, due to the concurrent nature of VHDL, and a uniform hardware netlist format for all design and test applications. In this paper, the general methodologies for using VHDL in testing are presented and a specific example for adaptive random test generation is explained in detail.","PeriodicalId":212876,"journal":{"name":"Proceedings VHDL International Users' Forum. Fall Conference","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1997-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Implementing a complete test tool set in VHDL\",\"authors\":\"A. Peymandoust, Z. Navabi\",\"doi\":\"10.1109/VIUF.1997.623923\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"As a concurrent programming environment, VHDL can be used for the implementation of most digital system test algorithms for test generation and fault simulation. The benefits are in easier implementations, due to the concurrent nature of VHDL, and a uniform hardware netlist format for all design and test applications. In this paper, the general methodologies for using VHDL in testing are presented and a specific example for adaptive random test generation is explained in detail.\",\"PeriodicalId\":212876,\"journal\":{\"name\":\"Proceedings VHDL International Users' Forum. Fall Conference\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-10-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings VHDL International Users' Forum. Fall Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VIUF.1997.623923\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings VHDL International Users' Forum. Fall Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VIUF.1997.623923","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
As a concurrent programming environment, VHDL can be used for the implementation of most digital system test algorithms for test generation and fault simulation. The benefits are in easier implementations, due to the concurrent nature of VHDL, and a uniform hardware netlist format for all design and test applications. In this paper, the general methodologies for using VHDL in testing are presented and a specific example for adaptive random test generation is explained in detail.
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