Reducing FPGA design modification time

An incremental approach to logic synthesis developed under the RASSP program is described. The approach reduces the time it takes to implement changes in an FPGA design. It also helps designers stay connected with the implementation issues and helps new synthesis users get over the learning curve. It involves resynthesizing only the blocks of the design that change, rather than the whole design. Existing blocks of unmodified logic are reused through the netlist merge capabilities of many foundry tools. Results show that the incremental approach helps speed up the total design cycle time.