Proposing graphic extensions to VHDL

VHDL is a text-based hardware description language but, traditionally, graphical representation was used for describing the structure and the architecture of hardware. Even today, the leading tools offer some graphical design entry and thus a graphical representation of its models. In general, these representations are not compatible to each other and, when transferring the VHDL model from one toolset to another, the graphical representation is lost. Also, when introducing an audience to a new hardware concept, the graphical representation helps for an easy understanding of the presented concepts. A solution to this situation would be to define a standard graphical representation for VHDL constructs. The graphical representation could be restricted to a standard representation of structural constructs. The graphical representation of behavioral constructs could be made open to the tool vendors. This definition does not require a change of VHDL in itself. A similar approach was taken to the formal description languages SDL and MSC, which have, besides their textual representation, a graphical representation. The author has had good experiences with SDL, which is a formal description technique. The language is powerful, has a growing acceptance and is well suited for hardware/software codesign. Based on this experience, the proposal for a graphical representation of VHDL is presented in this paper. The paper starts with a short introduction to SDL, followed by a demonstration of how graphic constructs could increase the acceptance of VHDL.