Advanced Lithography最新文献_第9页

Middle-of-line plasma dry etch challenges for CFET integration 中线等离子体干蚀刻对CFET集成的挑战

Advanced Lithography Pub Date : 2023-05-01 DOI: 10.1117/12.2659095

D. Radisic, M. Hosseini, H. Mertens, D. Zhou, V. Vega Gonzalez, S. Wang, B. Chan, D. Batuk, E. Dupuy, Z. Tao, E. Dentoni Litta, N. Horiguchi

{"title":"Middle-of-line plasma dry etch challenges for CFET integration","authors":"D. Radisic, M. Hosseini, H. Mertens, D. Zhou, V. Vega Gonzalez, S. Wang, B. Chan, D. Batuk, E. Dupuy, Z. Tao, E. Dentoni Litta, N. Horiguchi","doi":"10.1117/12.2659095","DOIUrl":"https://doi.org/10.1117/12.2659095","url":null,"abstract":"In this paper, middle-of-line (MOL) plasma etch development results for the monolithic CFET integration with nanosheet devices using scaling-relevant test vehicle (CPP48nm) are presented. Several critical MOL patterning steps are addressed, with the focus on the patterning of the trenches (M0) for contacting to the bottom and top devices. The patterning of M0A consists of SiO2 dielectric and thin SiN liner etch landing on epitaxial source drain (S/D). The critical M0 etch requirement is preserving the SiN gate spacer to avoid shorting between S/D and gate. Due to no-gate plug implementation in the process flow, the etch development must rely on very challenging, patterning the small critical dimension (CD) contacts to create enough dielectric barrier between the metal contact and the gate, and preferably, also very challenging, self-alignment to the thin gate spacer. The dependance of the M0 CD and the etch depth is accessed by using the range of the EUV lithography conditions and evaluating the maximum etch depth of the trench as a function of the printed CD. The minimum trench CD achieved on the bottom of the trench is ~ 13nm, and the minimum top CD in the range of ~ 16nm, with the evident etch non-uniformity observed in the etch depth. The trend of larger contact CD resulting in the deeper etch and process uniformity improvement is observed. Etch depth larger than 100nm is achieved when top M0 CD is >20nm. The option with the SiN liner deposition followed by SiN liner etch (spacer formation) post- M0 SiO2 is developed. This patterning sequence consists of SiO2 etch stopping on the thin SiN (over S/D) followed by additional SiN deposition and finally etching of the deposited SiN liner as well as SiN liner covering S/D. The option with SiN spacer formation minimizes the risk of short to the gate, due to extra SiN dielectric film protecting the gate. In addition, we present the results for another critical MOL patterning step, i.e., HAR metal recess post M0 metallization (AR~11)","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131510802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Understanding etch properties of advanced chemically amplified EUV resist 了解先进化学放大EUV抗蚀剂的蚀刻性能

Advanced Lithography Pub Date : 2023-05-01 DOI: 10.1117/12.2659178

J. Park, E. Aqad, Yinjie Cen, S. Coley, Li Cui, Conner A. Hoelzel, Benjamin Naab, Choong-Bong Lee, Rochelle Rena, Philjae Kang, Y. Shin, David Limberg, Lei Zhang

{"title":"Understanding etch properties of advanced chemically amplified EUV resist","authors":"J. Park, E. Aqad, Yinjie Cen, S. Coley, Li Cui, Conner A. Hoelzel, Benjamin Naab, Choong-Bong Lee, Rochelle Rena, Philjae Kang, Y. Shin, David Limberg, Lei Zhang","doi":"10.1117/12.2659178","DOIUrl":"https://doi.org/10.1117/12.2659178","url":null,"abstract":"Extreme ultraviolet (EUV) lithography technology empowers integrated circuit industry to mass produce chips with smaller pitches and higher density. Along with EUV tool advancement, significant progress has also been made in the development and advancement of EUV chemically amplified resist (CAR) materials, which allows for the improvement of resolution, line edge roughness, and sensitivity (RLS) trade-off. The scarce number of EUV photons has triggered the development of resist material with high absorption at 13.5 nm. However, a review of open literature reveals very limited reports on the effect of high EUV absorption elements on etch properties of advanced EUV resist. To ensure Moore’s Law continues to move forward, further resist performance improvement is required. In this regard, stochastic defects originating from photon shot noise, materials, and processing variabilities present a unique challenge for the extension of CAR platform for the patterning of smaller nodes. Notably, less attention has been paid to defects formed during the etching process used for pattern transfer. In this paper, we report on the relationship between resist make-up and etch properties. In particular, the effect of incorporation of EUV high absorbing elements are examined. New resist material design strategies for continuous improvement of EUV CAR lithographic performance will be discussed.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133199241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Selective isotropic atomic-layer etching of thin films by using dry chemical removal tool 用干法化学去除工具对薄膜进行选择性各向同性原子层蚀刻

Advanced Lithography Pub Date : 2023-05-01 DOI: 10.1117/12.2664547

Kazunori Shinoda, Nobuya Miyoshi, Hiroyuki Kobayashi, M. Izawa, K. Ishikawa, M. Hori

{"title":"Selective isotropic atomic-layer etching of thin films by using dry chemical removal tool","authors":"Kazunori Shinoda, Nobuya Miyoshi, Hiroyuki Kobayashi, M. Izawa, K. Ishikawa, M. Hori","doi":"10.1117/12.2664547","DOIUrl":"https://doi.org/10.1117/12.2664547","url":null,"abstract":"There has been considerable interest in the development of isotropic atomic layer etching (ALE) for the conformal removal of thin films. Material selectivity is crucial for the development of isotropic ALE because the next generation of semiconductor devices will be constructed with miniaturized 3D structures using a variety of very thin films. We developed plasma-assisted thermal-cyclic ALE, which is a repetition of surface modification by plasma exposure and removal of the modified surface by infrared heating. We developed a 300-mm tool, namely, dry chemical removal (DCR), which is equipped with an inductively coupled plasma (ICP) source and infrared lamps, to facilitate rapid thermal desorption of the modified surface. An important feature of the plasma-assisted thermal-cyclic ALE is that it has more tuning knobs than that of conventional ALE because it uses two temperatures: a low temperature for surface modification and an elevated temperature for the removal of the modified surface. This paper presents the selective ALE of various materials, i.e., Si3N4, TiN, W, and SiGe using the developed tool. The mechanisms of the selectivity are divided into two categories: formation of an ammonium salt-based modified layer and selectivity control by adjusting the infrared heating time. This paper reviews the selective ALE mechanisms, focusing on the results of in situ analysis of surface reactions, and presents some of the latest findings.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114476547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Recent advances in EUV patterning in preparation towards high-NA EUV 高na极紫外制备技术的最新进展

Advanced Lithography Pub Date : 2023-05-01 DOI: 10.1117/12.2657432

S. Nagahara, Arnaud Dauendorffer, A. Thiam, Xiang Liu, Yuhei Kuwahara, C. Dinh, Soichiro Okada, S. Kawakami, H. Genjima, Noriaki Nagamine, M. Muramatsu, S. Shimura, A. Tsuboi, K. Nafus, Y. Feurprier, M. Demand, R. Ramaneti, P. Foubert, D. De Simone, Geert Vendenberghe

引用次数: 2

Predicting the critical features of the chemically-amplified resist profile based on machine learning 基于机器学习预测化学放大抗蚀剂特征的关键特征

Advanced Lithography Pub Date : 2023-05-01 DOI: 10.1117/12.2658664

Pengjie Kong, Lisong Dong, Xu Ma, Yayi Wei

引用次数: 0

Thin underlayer materials for metal oxide resist patterning 金属氧化物抗图案化的薄底层材料

Advanced Lithography Pub Date : 2023-05-01 DOI: 10.1117/12.2657918

Satoshi Dei, Yuya Hayashi, S. Akita, Shuhei Yamada, K. Sakai, Tatsuya Kasai, Akitaka Nii, Ayaka Furusawa, K. Takada, T. Kaneko, Tomoaki Seko, Eiji Yoneda, Tatsuya Sakai

引用次数: 0

Establishment of new process technology for EUV lithography EUV光刻新工艺技术的建立

Advanced Lithography Pub Date : 2023-05-01 DOI: 10.1117/12.2657076

Yuhei Kuwahara, S. Kawakami, Kanzo Kato, Soichiro Okada, Y. Kamei, T. Onitsuka, T. Yamauchi, Nanoka Miyahara, C. Dinh, L. Huli, S. Shimura

引用次数: 1

Challenges for spacer and source/drain cavity patterning in CFET devices CFET器件中间隔器和源/漏腔设计的挑战

Advanced Lithography Pub Date : 2023-05-01 DOI: 10.1117/12.2658073

G. Mannaert, H. Mertens, M. Hosseini, S. Demuynck, V. Nguyen, B. Chan, F. Lazzarino

{"title":"Challenges for spacer and source/drain cavity patterning in CFET devices","authors":"G. Mannaert, H. Mertens, M. Hosseini, S. Demuynck, V. Nguyen, B. Chan, F. Lazzarino","doi":"10.1117/12.2658073","DOIUrl":"https://doi.org/10.1117/12.2658073","url":null,"abstract":"In a complementary-FET (CFET), n- and p- type transistors are stacked on top of each other. This stacking approach results in very high aspect ratio vertical features which brings critical challenges for nanosheet (NSH), gate, spacer, and source/drain (S/D) cavity patterning. Silicon nitride spacers are commonly used to electrically isolate and protect the silicon gate during S/D epitaxial growth and to precisely define the channel length (Lg) [1-4]. In this work, we will discuss the spacer film opening, the optimization of the S/D cavity profile and propose options to reduce the gate hard mask consumption. We were able to straighten the S/D cavity profile in the SiGe superlattice substrate by tuning specific process parameters, during the various etch and over-etch steps of the stack. Chemical analysis of the sidewall of the cavity, by TEM/EDS, confirmed that the formation of a passivation oxi-nitride compound is key to achieve vertical cavity profile. The chemical mapping of the cavity was done through the Si and SiGe25% sheets. A Si, O and N containing passivation layer is present in the cavity which seems to be thicker at the top and thinner at the bottom of the cavity. Furthermore, polymer capping methods were investigated to reduce the consumption of oxide hard mask (HM) during spacer etch. Process optimization for the cavity shape in the S/D recess etch was conducted using TEM characterization.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128130473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Dissociative photoionization of EUV lithography photoresist models EUV光刻光刻胶模型的解离光电离

Advanced Lithography Pub Date : 2023-05-01 DOI: 10.1117/12.2657702

M. Gentile, M. Gerlach, R. Richter, M. V. van Setten, J. Petersen, P. van der Heide, F. Holzmeier

引用次数: 3

Fundamentals of EUV stack for improving patterning performance 提高图案化性能的EUV堆栈基础

Advanced Lithography Pub Date : 2023-05-01 DOI: 10.1117/12.2657056

Nanoka Miyahara, Soichiro Okada, Hiroyuki Fujii, S. Shimura

引用次数: 1