2022 25th Euromicro Conference on Digital System Design (DSD)最新文献_第8页

Open-Source Research on Time-predictable Computer Architecture 时间可预测计算机体系结构的开源研究

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00047

Martin Schoeberl

引用次数: 0

An FPGA based Tiled Systolic Array Generator to Accelerate CNNs 基于FPGA的平铺收缩阵列发生器加速cnn

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00050

Veerendra S. Devaraddi, N. Rao

{"title":"An FPGA based Tiled Systolic Array Generator to Accelerate CNNs","authors":"Veerendra S. Devaraddi, N. Rao","doi":"10.1109/DSD57027.2022.00050","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00050","url":null,"abstract":"The main computation in any CNN is convolution operation. This computation shows significant potential for massively parallel implementations on an FPGA. Systolic arrays with their intrinsic pipelining have been explored for CNN inference. In this paper, we present a systolic array architecture suitably designed for a novel method of convolution operation. We implement an image-kernel convolution and test it with representative image inputs to several models like LeNet-5, AlexNet, VGG-16, and Resnet-34. We compare the proposed design with conventional convolution and HLS based designs. We limit our implementation to resource constrained FPGA: AMD-Xilinx Zynq 7020 platform. We observe that the proposed architecture outperforms the direct convolution method and HLS pipelined designs by 2× and 2.1×, respectively, on average. Since DSP blocks are scarce resources, we constrain our implementation to avoid DSP blocks and use the LUTs instead. Thus, our implementation uses nearly 9× more LUTs than baseline convolution but 8× fewer LUTs than the HLS pipelined implementation. We further accelerate the convolution throughput by 11×. We achieve this by implementing a tiled systolic architecture that completely utilises the parallel computing resources of the FPGA.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"386 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133140643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

In vitro Testbed Platform for Evaluating Small Volume Contrast Agents via Magnetic Resonance Imaging 磁共振成像评价小体积造影剂的体外实验平台

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00082

Mireia Perera-Gonzalez, Kristine Y. Ma, C. Flask, H. Clark

{"title":"In vitro Testbed Platform for Evaluating Small Volume Contrast Agents via Magnetic Resonance Imaging","authors":"Mireia Perera-Gonzalez, Kristine Y. Ma, C. Flask, H. Clark","doi":"10.1109/DSD57027.2022.00082","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00082","url":null,"abstract":"Quantitative magnetic resonance imaging (MRI) is a non-invasive imaging method with high resolution and unlimited penetration depth. Contrast agents (CAs) can assist in disease diagnosis and tissue screening via MRI. In vitro characterization of CAs in development is often carried out using sample sizes in the milliliter range or higher. Particularly when reagent costs are high, MRI would benefit from a standard platform for precise quantification of small volume CAs (microliter scale), ultimately enabling translation from in vitro to in vivo applications. In this initial study, we developed and evaluated a microliter-scale concentric “MiSCo” testbed as a platform to optimize MRI quantification of small volume samples in vitro. The platform facilitated accurate, repeatable, and reproducible MRI quantitative measurements with a 5-fold and 30-fold increase in precision and signal-to-noise-ratio, respectively, when compared to more traditional configurations. We believe this approach could serve as a path for future improvements in the field of quantitative MRI, ensuring high sensitivity measurements of small volume CAs.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"87 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132657690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Ballast: Implementation of a Large MP-SoC on 22nm ASIC Technology 镇流器:在22nm ASIC技术上实现大型MP-SoC

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00045

Antti Rautakoura, Timo D. Hämäläinen, A. Kulmala, Tero Lehtinen, Mehdi Duman, Mohamed Ibrahim

引用次数: 2

RRAM-based Neuromorphic Computing: Data Representation, Architecture, Logic, and Programming 基于随机存储器的神经形态计算:数据表示、体系结构、逻辑和编程

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00063

Grace Li Zhang, Shuhang Zhang, Hai Li, Ulf Schlichtmann

引用次数: 0

POLAR: Performance-aware On-device Learning Capable Programmable Processing-in-Memory Architecture for Low-Power ML Applications POLAR:低功耗机器学习应用的性能感知设备学习可编程内存处理架构

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00125

Sathwika Bavikadi, Purab Ranjan Sutradhar, Mark A. Indovina, A. Ganguly, Sai Manoj Pudukotai Dinakarrao

{"title":"POLAR: Performance-aware On-device Learning Capable Programmable Processing-in-Memory Architecture for Low-Power ML Applications","authors":"Sathwika Bavikadi, Purab Ranjan Sutradhar, Mark A. Indovina, A. Ganguly, Sai Manoj Pudukotai Dinakarrao","doi":"10.1109/DSD57027.2022.00125","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00125","url":null,"abstract":"Improving the performance of real-time Traffic Sign Recognition (TSR) applications using Deep Learning (DL) algorithms such as Convolutional Neural Networks (CNN) on software platforms is challenging due to the sheer computational complexity of these algorithms. In this work, we adopt a hardware-software combined approach to address this issue. We introduce a data-centric Processing-in-Memory (PIM) architecture that leverages Look-up-Table (LUT)-based processing for minimal data movement and superior performance and efficiency. Despite the superior performance, the limited available memory in PIM makes it complex to deploy deep CNNs. We propose merging CNN layers in this work to meet the limited resource constraints. One specific challenge in the TSR is the continuous change in the deployed environment, which makes a CNN model train over static data, leading to performance degradation over time. To address these challenges, we introduce a lightweight, performance-aware Generative Adversarial Network (GAN)-based on-device learning on PIM architecture. This compact CNN on PIM architecture attains data-level parallelism and reduces pipelining delays and makes it easier for on-device training and inference. Evaluation is performed on multiple state-of-the-art DL networks such as LeNet, AlexNet, ResNet using the German Traffic Sign Recognition Benchmark (GTSRB) Dataset, and the Belgium Traffic Sign Dataset (BTSD). With the proposed learning technique, it is observed to achieve maximum accuracy of 92.8% and 89.27% on GTSRB, and BTSD datasets. Also, it is observed the proposed mechanism maintains an average accuracy to be above 85% despite changes in the environment on all the CNNs deployed on the PIM accelerator.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124121864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Is the Whole lesser than its Parts? Breaking an Aggregation based Privacy aware Metering Algorithm 整体比部分小吗?突破一种基于聚合的隐私感知计量算法

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00129

Soumyadyuti Ghosh, Urbi Chatterjee, Soumyajit Dey, Debdeep Mukhopadhyay

{"title":"Is the Whole lesser than its Parts? Breaking an Aggregation based Privacy aware Metering Algorithm","authors":"Soumyadyuti Ghosh, Urbi Chatterjee, Soumyajit Dey, Debdeep Mukhopadhyay","doi":"10.1109/DSD57027.2022.00129","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00129","url":null,"abstract":"Smart metering is a mechanism through which fine-grained electricity usage data of consumers is collected periodically in a smart grid. However, a growing concern in this regard is that the leakage of consumers' consumption data may reveal their daily life patterns as the state-of-the-art metering strategies lack adequate security and privacy measures. Many proposed solutions have demonstrated how the aggregated metering information can be transformed to obscure individual consumption patterns without affecting the intended semantics of smart grid operations. In this paper, we expose a complete break of such an existing privacy preserving metering scheme [10] by determining individual consumption patterns efficiently, thus compromising its privacy guarantees. The underlying methodol-ogy of this scheme allows us to - i) retrieve the lower bounds of the privacy parameters and ii) establish a relationship between the privacy preserved output readings and the initial input readings. Subsequently, we present a rigorous experimental validation of our proposed attacking methodology using real-life dataset to highlight its efficacy. In summary, the present paper queries: Is the Whole lesser than its Parts? for such privacy aware metering algorithms which attempt to reduce the information leakage of aggregated consumption patterns of the individuals.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"567 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116456255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Polynomial Formal Verification of Approximate Adders 近似加法器的多项式形式验证

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00107

Martha Schnieber, Saman Fröhlich, R. Drechsler

{"title":"Polynomial Formal Verification of Approximate Adders","authors":"Martha Schnieber, Saman Fröhlich, R. Drechsler","doi":"10.1109/DSD57027.2022.00107","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00107","url":null,"abstract":"To ensure the functional correctness of digital circuits, formal verification methods have been established, where the circuits are proven to implement the correct function. Several methods exist for the execution of the verification process. However, the verification process can have an exponential time or space complexity, causing the verification to fail. While exponen-tial in general, recently it has been proven that the verification complexity of several circuits is polynomially bounded. In this paper, we prove the polynomial verifiability of several state-of-the-art approximate adders using BDDs. These approx-imate adders include handcrafted approximate adders, which consist of several subadders, as well as automatically generated approximate adders, where regular adders can be arbitrarily altered by removing gates and changing the type of gates. Thus, this paper provides insight into the possible methods for the design of approximate adders, such that the approximate adders remain polynomially verifiable. Here, we give upper bounds for the BDD sizes during the verification process, as well as for the time and space complexity. The upper bounds for the BDD sizes are then experimentally evaluated.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122775694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Placement of Chains of Real-Time Tasks on Heterogeneous Platforms under EDF Scheduling EDF调度下异构平台上实时任务链的布置

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00029

Daniel Casini, Alessandro Biondi

{"title":"Placement of Chains of Real-Time Tasks on Heterogeneous Platforms under EDF Scheduling","authors":"Daniel Casini, Alessandro Biondi","doi":"10.1109/DSD57027.2022.00029","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00029","url":null,"abstract":"When designing a real-time system, application architects are called to settle many non-trivial decisions that may severely influence the system's performance. With modern hardware platforms always being more and more complex and equipped with heterogeneous processor cores or even hardware accelerators such as TPUs, FPGAs, or GPUs, the complexities to be faced by application architects are exacerbated. Therefore, they are called to wisely allocate the computational resources provided by the hardware platform to application tasks in such a way to meet timing requirements and optimize other goals such as energy consumption. This paper proposes a mixed-integer linear programming formulation (MILP) to solve the task-to-heterogeneous-cores allocation problem while guaranteeing the schedulability of a real-time application running on the platform under partitioned Earliest Deadline First (EDF) scheduling. A new method to derive approximate worst-case response-time bounds is also presented and leveraged to setup the MILP formu-lation, which allows computing and minimizing the end-to-end latency of processing chains and considers energy requirements. The approach is evaluated on a task set based on the WATERS 2019 Industrial Challenge proposed by Bosch.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125007033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

TextBack: Watermarking Text Classifiers using Backdooring TextBack:水印文本分类器使用后门

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00053

Nandish Chattopadhyay, Rajan Kataria, A. Chattopadhyay

{"title":"TextBack: Watermarking Text Classifiers using Backdooring","authors":"Nandish Chattopadhyay, Rajan Kataria, A. Chattopadhyay","doi":"10.1109/DSD57027.2022.00053","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00053","url":null,"abstract":"Creating high performance neural networks is ex-pensive, incurring costs that can be attributed to data collection and curation, neural architecture search and training on dedi-cated hardware accelerators. Stakeholders invested in any one or more of these aspects of deep neural network training expect as-surances on ownership and guarantees that unauthorised usage is detectable and therefore preventable. Watermarking the trained neural architectures can prove to be a solution to this. While such techniques have been demonstrated in image classification tasks, we posit that a watermarking scheme can be developed for natural language processing applications as well. In this paper, we propose TextBack, which is a watermarking technique developed for text classifiers using backdooring. We have tested for the functionality preserving properties and verifiable proof of ownership of TextBack on multiple neural architectures and datasets for text classification tasks. The watermarked models consistently generate accuracies within a range of 1 - 2% of models without any watermarking, whilst being reliably verifiable during watermarking verification. TextBack has been tested on two different kinds of Trigger Sets, which can be chosen by the owner as preferred. We have studied the efficiencies of the algorithm that embeds the watermarks by fine tuning using a combination of Trigger samples and clean samples. The benefit of using TextBack's fine tuning approach on pre-trained models from a computational cost perspective against embedding watermarks by training models from scratch is also established experimentally. This watermarking scheme is not computation intensive and adds no additional burden to the neural architecture. This makes TextBack suitable for lightweight applications on edge devices as the watermarked model can be deployed on resource-constrained hardware and SoCs when required.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128789060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0