2022 25th Euromicro Conference on Digital System Design (DSD)最新文献_第7页

On the Characterization of Jitter in Ring Oscillators using Allan variance for True Random Number Generator Applications 用Allan方差表征环振抖动在真随机数发生器中的应用

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00077

L. Benea, M. Carmona, Florian Pebay-Peyroula, R. Wacquez

{"title":"On the Characterization of Jitter in Ring Oscillators using Allan variance for True Random Number Generator Applications","authors":"L. Benea, M. Carmona, Florian Pebay-Peyroula, R. Wacquez","doi":"10.1109/DSD57027.2022.00077","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00077","url":null,"abstract":"The description of the physical noise source is of utmost importance for any TRNG certification. In the case of ring oscillators, Allan variance is a reliable and comprehensive tool which enables the distinction between the jitter coming from flicker noise (autocorrelated) and from thermal noise (random). In this paper, we realize measurements directly on the analog source of numerous TRNG structures: a ring oscillator. Our data, along with evidence from the literature, indicates the presence of a third noise source. The quantization noise has not been so far taken into consideration, but is unquestionably present in all TRNG reliant on jitter. Its importance is key to an accurate estimation of thermal noise contribution, which can be shadowed by it. Measurements presented in this paper show that insufficient sampling (i.e. higher quantization noise) can lead to an overestimation of jitter coming from thermal noise and therefore an overestimation of the calculated entropy. The latter is the only type of noise considered reliable in currently existing ring oscillator-based TRNG models. As a rule of thumb, three orders of magnitude between the sampling and the sampled signal are necessary in order to determine the thermal noise jitter correctly.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131855064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Attention-based Skin Cancer Classification Through Hyperspectral Imaging 基于关注的高光谱成像皮肤癌分类

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00122

M. L. Salvia, E. Torti, M. Gazzoni, E. Marenzi, Raquel León, S. Ortega, H. Fabelo, G. Callicó, F. Leporati

引用次数: 1

Design Space Exploration for Distributed Cyber-Physical Systems: State-of-the-art, Challenges, and Directions 分布式信息物理系统的设计空间探索:最新技术、挑战和方向

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00090

Marius Herget, Faezeh Sadat Saadatmand, Martin C. Bor, Ignacio Gonzalez Alonso, T. Stefanov, B. Akesson, A. Pimentel

引用次数: 0

PosAx-O: Exploring Operator-level Approximations for Posit Arithmetic in Embedded AI/ML PosAx-O:探索嵌入式AI/ML中位置算法的算子级近似

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00037

Amritha Immaneni, Salim Ullah, S. Nambi, Siva Satyendra Sahoo, Akash Kumar

{"title":"PosAx-O: Exploring Operator-level Approximations for Posit Arithmetic in Embedded AI/ML","authors":"Amritha Immaneni, Salim Ullah, S. Nambi, Siva Satyendra Sahoo, Akash Kumar","doi":"10.1109/DSD57027.2022.00037","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00037","url":null,"abstract":"The quest for low-cost embedded AI/ML applications has motivated innovations across multiple abstractions of the computation stack. Novel approaches for arithmetic operations have primarily involved quantization, precision-scaling, approximations, and modified data representation. In this context, Posit has emerged as an alternative to the IEEE-754 standard as it offers multiple benefits, primarily due to its dynamic range and tapered precision. However, the implementation of Posit arithmetic operations tends to result in high resource utilization and power dissipation. Consequently, recent works have delved into the idea of exploiting the error resilience of machine learning algorithms by using low-precision Posit arithmetic. However, limiting the exploration to precision-scaling limits the scope for application-specific optimizations for embedded AI/ML applications. To this end, we explore operator-level optimizations and approximations for low-precision Posit numbers. Specifically, we identify and eliminate redundant operations in state-of-the-art Posit arithmetic operator designs and provide a modular framework for exploring approximations in various stages of the computation. We also present a novel framework for behaviorally testing the corresponding Posit approximate designs in Artificial Neural Networks. The proposed optimizations and approximations exhibit considerable resource improvements with a small error in many cases. For instance, a Posit-based multiplier with 1-bit reduced precision shows a 33% improvement in power and utilization, with only a 0.2% degradation in overall accuracy.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114327184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

SmartDelta: Automated Quality Assurance and Optimization in Incremental Industrial Software Systems Development SmartDelta:增量工业软件系统开发中的自动化质量保证和优化

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00106

Mehrdad Saadatmand, Eduard Paul Enoiu, H. Schlingloff, M. Felderer, W. Afzal

引用次数: 3

Real-Time Polling Task: Design and Analysis 实时轮询任务:设计与分析

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00089

Benoit Varillon, D. Doose

引用次数: 0

Optimizing Lattice-based Post-Quantum Cryptography Codes for High-Level Synthesis 高阶合成中基于格子的后量子密码码优化

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00109

Andrea Guerrieri, Gabriel Da Silva Marques, F. Regazzoni, A. Upegui

引用次数: 0

Mobile Systems Secure State Management 移动系统安全状态管理

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00081

P. Amato, Niccolò Izzo, Carlo Meijer

{"title":"Mobile Systems Secure State Management","authors":"P. Amato, Niccolò Izzo, Carlo Meijer","doi":"10.1109/DSD57027.2022.00081","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00081","url":null,"abstract":"Today's mobile devices are equipped with sophis-ticated chain-of-trust mechanisms, able to successfully mitigate tampering of critical software components. However, this tech-nology, on the one hand, hinders the permanence of malware, thus raising the complexity for developing rootkits. On the other hand, the freedom of the end-user is limited. In fact, with all the security features enabled, one could not run any privileged code without it being signed by the Original Equipment Manufacturer; modifying any component of the root partition would cause a device read error and small modifications could be even rolled back automatically. Original Equipment Manufacturers typically provide mechanisms to (partially) disable these security features. However, they usually require two conditions: every unlock request must be approved by them, e.g. for warranty implications; secondly, to preserve the device security level, each time a security feature is disabled, the user data must be completely erased. We analyze several bootloader related vulnerabilities which allow to bypass these two requirements by exploiting design and implementation flaws in smartphones from different vendors. We then propose a novel architecture for secure device status storage and management. Our proposal relies only on commodity hardware features, which can be found on most mobile platforms. Furthermore, differently from many commercial implementations, we do not consider the storage device firmware as trusted, this makes our attack surface smaller than all of the examined alternatives.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127578865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

FP-SLIC: A Fully-Pipelined FPGA Implementation of Superpixel Image Segmentation FP-SLIC:一种全流水线FPGA实现的超像素图像分割

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00024

A. Ghaderi, C. Ahlberg, Magnus Östgren, F. Ekstrand, Mikael Ekström

引用次数: 0

MEDA Biochip based Single- Target Fluidic Mixture Preparation with Minimum Wastage 基于MEDA生物芯片的单目标流体混合物制备的最小浪费

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00113

Debraj Kundu, Sudip Roy

{"title":"MEDA Biochip based Single- Target Fluidic Mixture Preparation with Minimum Wastage","authors":"Debraj Kundu, Sudip Roy","doi":"10.1109/DSD57027.2022.00113","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00113","url":null,"abstract":"Sample preparation is an inherent procedure of many biochemical applications, and digital microfluidic biochips (DMBs) proved to be very effective in performing such a procedure. In a single mixing step, conventional DMBs can mix two droplets in 1:1 ratio only. Due to this limitation, DMBs suffer from heavy fluid wastage and large number of mixing steps. However, the next generation DMBs, i.e., micro-electrode-dot-array (MEDA) biochips can realize multiple mixing ratios and are able to overcome a lot of those limitations. In this paper, we present a heuristic-based sample preparation algorithm, specifically a mixing algorithm called Division by Factor Method for Mixing that exploits the mixing models of MEDA biochips. We propose another mixing algorithm for MEDA biochips called Single Target Waste Minimization (STWM), which minimizes the wastage of fluids and determines an optimized mixing graph. Simulation results confirm that the proposed STWM method outperforms the state-of-the-art method in terms of minimizing the number of waste fluids, reducing the total reagent usage, and minimizing the number of mixing operations.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117115901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1