2022 25th Euromicro Conference on Digital System Design (DSD)最新文献

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A resolution method in case of air congestion: rerouting and/or ground holding approach 一种解决空气堵塞的方法:改变航线和/或地面等待进近
2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00123
L. Adacher, M. Flamini
{"title":"A resolution method in case of air congestion: rerouting and/or ground holding approach","authors":"L. Adacher, M. Flamini","doi":"10.1109/DSD57027.2022.00123","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00123","url":null,"abstract":"This paper deals with the problem of congestion in air transportation systems. Congestion occurs when demand for the infrastructures exceeds their capacity, causing delays as one of the main drawbacks. Congestion can be solved by applying ground holding and/or rerouting flights operations. Such procedures often imply delays and a series of significant reactionary costs for all the operators of the air traffic management. In this paper authors propose a method to solve the congestion by an optimizaion algorithm combining the ground holding and/or rerouting operations. Aircraft rerouting is performed by a tailored shortest path algorithm. A real portion of the air traffic network and a real slice of the air traffic flow have been considered for the experiments.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129656171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Implementation of the Rainbow signature scheme on SoC FPGA 彩虹签名方案在SoC FPGA上的实现
2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00074
Tomás Preucil, Petr Socha, M. Novotný
{"title":"Implementation of the Rainbow signature scheme on SoC FPGA","authors":"Tomás Preucil, Petr Socha, M. Novotný","doi":"10.1109/DSD57027.2022.00074","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00074","url":null,"abstract":"Thanks to the research progress, quantum computers are slowly becoming a reality and some companies already have their working prototypes. While this is great news for some, it also means that some of the encryption algorithms used today will be rendered unsafe and obsolete. Due to this fact, NIST (US National Institute of Standards and Technology) has been running a standardization process for quantum-resistant key exchange algorithms and digital signatures. One of these is Rainbow—a signature scheme based on the fact that solving a set of random multivariate quadratic system is an NP-hard problem. This work aims to develop an AXI-connected accelerator for the Rainbow signature scheme, specifically the Ia variant. The accelerator is highly parameterizable, allowing to choose the data bus width, directly affecting the FPGA area used. It is also possible to swap components to use the design for other variants of Rainbow. This allows for a comprehensive experimental evaluation of our design. The developed accelerator provides significant speedup compared to CPU-based computation. This paper includes detailed documentation of the design as well as performance and resource utilisation evaluation.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132625414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Monitoring Framework to Support Mixed-Criticality Applications on Multicore Platforms 支持多核平台上混合关键应用的监控框架
2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00092
Gautam Gala, Carlos Rodriguez, Gabriele Monaco, Javier Castillo, G. Fohler, Veaceslav Falico, S. Tverdyshev
{"title":"Monitoring Framework to Support Mixed-Criticality Applications on Multicore Platforms","authors":"Gautam Gala, Carlos Rodriguez, Gabriele Monaco, Javier Castillo, G. Fohler, Veaceslav Falico, S. Tverdyshev","doi":"10.1109/DSD57027.2022.00092","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00092","url":null,"abstract":"The automotive industry is looking into integrated architecture to combine multiple application subsystems of different criticalities on the readily available low-cost multicore platforms as they promise several benefits. However, it is difficult to achieve the required isolation and guarantees in such an architecture due to contention in shared resources, e.g., CPU, shared-bus, and memory (controller). This can cause unpredictable delays leading to deadline misses in real-time applications. We propose a low overhead modular monitoring framework to provide support for ensuring that the real-time applications meet their deadline when considering shared resource accesses, and helping to improve resource utilization so that best-effort applications can achieve a better Quality-of-Service despite pessimistic resource allocation assumptions of real-time applications. Our framework keeps the monitoring overheads to a minimum and triggered reaction meaningful by operating on the basis of low-level hardware and software signals, strategically checking resources, and triggering actions based on abstract availability of resources. We propose a Domain-Specific Language (DSL) to relieve the system designers from the tedious and error-prone job of configuring platform-specific parameters for the framework. Finally, this paper evaluates our monitoring framework based on an instantiation on a Xilinx Zynq UltraSacle multicore SoC running Linux and a simple industry-inspired use case.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133457236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Analysis of Graph Processing in Reconfigurable Devices for Edge Computing Applications 边缘计算应用中可重构设备的图形处理分析
2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00012
Kaan Olgu, Kris Nikov, J. Núñez-Yáñez
{"title":"Analysis of Graph Processing in Reconfigurable Devices for Edge Computing Applications","authors":"Kaan Olgu, Kris Nikov, J. Núñez-Yáñez","doi":"10.1109/DSD57027.2022.00012","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00012","url":null,"abstract":"Graph processing is an area that has received significant attention in recent years due to the substantial expansion in industries relying on data analytics. Alongside the vital role of finding relations in social networks, graph processing is also widely used in transportation to find optimal routes and biological networks to analyse sequences. The main bottleneck in graph processing is irregular memory accesses rather than computation intensity. Since computational intensity is not a driving factor, we propose a method to perform graph processing at the edge more efficiently. We believe current cloud computing solutions are still very costly and have latency issues. The results demonstrate the benefits of a dedicated sparse graph processing algorithm compared with dense graph processing when analysing data with low density. As graph datasets grow exponentially, traversal algorithms such as breadth-first search (BFS), fundamental to many graph processing applications and metrics, become more costly to compute. Our work focuses on reviewing other implementations of breadth-first search algorithms designed for low power systems and proposing our solution that utilises advanced enhancements to achieve a significant performance boost up to 9.2x better performance in terms of MTEPS compared to other state-of-the-art solutions with a power usage of 2.32W.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116456117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Abeto framework: a Solution for Heterogeneous IP Management Abeto框架:异构IP管理的解决方案
2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00101
Antonio J. Sánchez, Y. Barrios, D. Ventura, Lucana Santos, R. Sarmiento
{"title":"Abeto framework: a Solution for Heterogeneous IP Management","authors":"Antonio J. Sánchez, Y. Barrios, D. Ventura, Lucana Santos, R. Sarmiento","doi":"10.1109/DSD57027.2022.00101","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00101","url":null,"abstract":"The use of third-party IP cores tends to present difficulties because of a lack of standardization in their packaging, distribution and management. Often, IP users find themselves writing code to enable the integration or testing of the IP core, which is not available as part of their distribution. In this work Abeto is presented, a new software tool for IP core databases management. It has been conceived to integrate and use a heterogeneous group of IP cores, described in HDL, with an unified set of instructions. In order to do so, Abeto requires from every IP core some side information about its packaging and how to operate with the IP. Currently, Abeto provides support for a set of common EDA tools and has been successfully applied to the European Space Agency portfolio of IP cores for benchmarking purposes. To demonstrate this extent, implementation results for these IP cores on the NanoXplore BRAVE FPGA family are provided, obtained through Abeto.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127154175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Side-Channel Analysis of Saber KEM Using Amplitude-Modulated EM Emanations 基于调幅电磁辐射的军刀KEM侧信道分析
2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00071
Ruize Wang, Kalle Ngo, E. Dubrova
{"title":"Side-Channel Analysis of Saber KEM Using Amplitude-Modulated EM Emanations","authors":"Ruize Wang, Kalle Ngo, E. Dubrova","doi":"10.1109/DSD57027.2022.00071","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00071","url":null,"abstract":"In the ongoing last round of NIST's post-quantum cryptography standardization competition, side-channel analysis of finalists is a main focus of attention. While their resistance to timing, power and near field electromagnetic (EM) side-channels has been thoroughly investigated, amplitude-modulated EM emanations has not been considered so far. The attacks based on amplitude-modulated EM emanations are more stealthy because they exploit side-channels intertwined into the signal transmitted by the on-board antenna. Thus, they can be mounted on a distance from the device under attack. In this paper, we present the first results of an amplitude-modulated EM side-channel analysis of one of the NIST PQ finalists, Saber key encapsulation mechanism (KEM), implemented on the nRF52832 (ARM Cortex-M4) system-on-chip supporting Bluetooth 5. By capturing amplitude-modulated EM emanations during decapsulation, we can recover each bit of the session key with 0.91 probability on average.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114777007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A Low-complexity FPGA TDC based on a DSP Delay Line and a Wave Union Launcher 基于DSP延迟线和波联合启动器的低复杂度FPGA TDC
2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00023
Zijie Wang, Jiajun Lu, J. Núñez-Yáñez
{"title":"A Low-complexity FPGA TDC based on a DSP Delay Line and a Wave Union Launcher","authors":"Zijie Wang, Jiajun Lu, J. Núñez-Yáñez","doi":"10.1109/DSD57027.2022.00023","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00023","url":null,"abstract":"High-precision time-to-digital converters (TDCs) are key components for controlling quantum systems and FPGAs have gained popularity for this task thanks to their low-cost and flexibility compared with Application Specific Integrated Circuits (ASICs). This paper investigates a novel FPGA-based TDC architecture that combines a wave union launcher and delay lines constructed with DSP blocks. The configuration achieves a 8.07ps RMS resolution on a low-cost Zynq FPGA with a power usage of only 0.628W. The low power consumption is achieved thanks to a combination of operating frequency and logic resource usage that are lower than other methods, such as multi-chain DSP based TDCs and multi-chain CARRY4 based TDCs.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114955781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
AxE: An Approximate-Exact Multi-Processor System-on-Chip Platform 一个近似精确的多处理器片上系统平台
2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00018
A. S. Baroughi, Sini Huemer, H. Shahhoseini, N. Taherinejad
{"title":"AxE: An Approximate-Exact Multi-Processor System-on-Chip Platform","authors":"A. S. Baroughi, Sini Huemer, H. Shahhoseini, N. Taherinejad","doi":"10.1109/DSD57027.2022.00018","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00018","url":null,"abstract":"Due to the ever-increasing complexity of computing tasks, emerging computing paradigms that increase efficiency, such as approximate computing, are gaining momentum. However, so far, the majority of proposed solutions for hardware-based approximation have been application-specific and/or limited to smaller units of the computing system and require engineering effort for integration into the rest of the system. In this paper, we present Approximate and Exact Multi-Processor system-on-chip (AxE) platform. AxE is the first general-purpose approximate Multi-Processor System-on-Chip (MPSoC). AxE is a heterogeneous RISC-V platform with exact and approximate cores that allows exploring hardware approximation for any application and using software instructions. Using the full capacity of an entire MPSoC, especially a heterogeneous one such as AxE, is an increasingly challenging problem. Therefore, we also propose a task mapping method for running exact and approximable applications on AxE. That is a mixed task mapping, in which applications are viewed as a set of tasks that can be run independently on different processors with different capabilities (exact or approximate). We evaluated our proposed method on AxE and reached a 32% average execution speed-up and 21% energy consumption saving with an average of 99.3% accuracy on three mixed workloads. We also ran a sample image processing application, namely gray-scale filter, on AxE and will present its results.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125178320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Variable-Length Instruction Set: Feature or Bug? 变长指令集:特点还是缺陷?
2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00068
Ihab Alshaer, Brice Colombier, C. Deleuze, V. Beroulle, P. Maistri
{"title":"Variable-Length Instruction Set: Feature or Bug?","authors":"Ihab Alshaer, Brice Colombier, C. Deleuze, V. Beroulle, P. Maistri","doi":"10.1109/DSD57027.2022.00068","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00068","url":null,"abstract":"With the increasing complexity of digital applications, the use of variable-length instruction sets became essential, in order to achieve higher code density and thus better performance. However, security aspects must always be considered, in particular with the significant improvement of attack techniques and equipment. Fault injection, in particular, is among the most interesting and promising attack techniques thanks to the recent advancements. In this article, we provide proper characterization, at the instruction set architecture (ISA) level, for several faulty behaviors that can be obtained when targeting a variable-length instruction set. We take into account the binary encoding of instructions, and show how the obtained behaviors depend on the alignment of the instructions in the memory. Moreover, we are also able to give a better insight on previous results from the literature, that were still partially unexplained. We also show how the observed behaviors can be exploited in various security contexts.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"10 10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122442440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
SNAP: Selective NTV Heterogeneous Architectures for Power-Efficient Edge Computing SNAP:用于高能效边缘计算的选择性NTV异构架构
2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00055
R. Tonetto, A. C. S. Beck, G. Nazar
{"title":"SNAP: Selective NTV Heterogeneous Architectures for Power-Efficient Edge Computing","authors":"R. Tonetto, A. C. S. Beck, G. Nazar","doi":"10.1109/DSD57027.2022.00055","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00055","url":null,"abstract":"While there is a growing need to process ML inference on the edge for improved latency and extra security, general-purpose solutions alone cannot cope with the increasing performance demand under power restrictions. Considering that systolic arrays are a prominent, but also power-hungry solution, we propose a methodology to enable their use in edge devices. For that, we propose SNAP, a selective Near-Threshold Voltage (NTV) strategy to explore heterogeneous MPSoCs with two voltage islands, one at NTV, and another at nominal voltage. By adopting a dynamic programming approach, SNAP may selectively apply NTV to the systolic array and to an optimal subset of cores in RISC- V-based MPSoCs, enabling ML acceleration on the edge. Combined with a smart application mapping, the strategy increases performance by up to 18.9 % over a nominal design within the same power limits.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114212237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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