2022 25th Euromicro Conference on Digital System Design (DSD)最新文献

{"title":"A resolution method in case of air congestion: rerouting and/or ground holding approach","authors":"L. Adacher, M. Flamini","doi":"10.1109/DSD57027.2022.00123","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00123","url":null,"abstract":"This paper deals with the problem of congestion in air transportation systems. Congestion occurs when demand for the infrastructures exceeds their capacity, causing delays as one of the main drawbacks. Congestion can be solved by applying ground holding and/or rerouting flights operations. Such procedures often imply delays and a series of significant reactionary costs for all the operators of the air traffic management. In this paper authors propose a method to solve the congestion by an optimizaion algorithm combining the ground holding and/or rerouting operations. Aircraft rerouting is performed by a tailored shortest path algorithm. A real portion of the air traffic network and a real slice of the air traffic flow have been considered for the experiments.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129656171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Generation of Verified Programs for In-Memory Computing","authors":"Saman Froehlich, R. Drechsler","doi":"10.1109/DSD57027.2022.00114","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00114","url":null,"abstract":"In order to overcome the von Neumann bottleneck, recently the paradigm of in-memory computing has emerged. Here, instead of transferring data from the memory to the CPU for computation, the computation is directly performed within the memory. ReRAM, a resistance-based storage device, is a promising technology for this paradigm. Based on ReRAM, the PLiM computer architecture and LiM-HDL, an HDL for specifying PLiM programs have emerged. In this paper, we first present a novel levelization algorithm for LiM-HDL. Based on this novel algorithm, large circuits can be compiled to PLiM programs. Then, we present a verification scheme for these programs. This scheme is separated into two steps: (1) A proof of purity and (2) a proof of equivalence. Finally, in the experiments, we first apply our levelization algorithms to a well-known benchmark set, where we show that we can generate PLiM programs for large benchmarks, for which existing levelization algorithms fails. Then, we apply our proposed verification scheme to these PLiM programs.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122654848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"RED-SEA: Network Solution for Exascale Architectures","authors":"A. Biagioni, P. Cretaro, O. Frezza, F. L. Cicero, A. Lonardo, Michele Martinelli, P. Paolucci, E. Pastorelli, F. Simula, Matteo Turisini, P. Vicini, R. Ammendola, Pascale Bernier-Bruna, Claire Chen, Said Derradji, Stephane Guez, Pierre-Axel Lagadec, G. Pichon, Etienne Walter, G. D. Gassowski, Matthieu Hautreaux, Stephane Mathieu, G. Moreau, Marc Pérache, Hugo Taboada, T. Hoefler, Timo Schneider, Matteo Barnaba, G. Brandino, F. D. Giorgi, Matteo Poggi, I. Mavroidis, Y. Papaefstathiou, N. Tampouratzis, Benjamin Kalisch, U. Krackhardt, Mondrian Nuessle, Pantelis Xirouchakis, Vangelis Mageiropoulos, Michalis Gianioudis, Harisis Loukas, Aggelos D. Ioannou, Nikos Kallimanis, N. Chrysos, M. Katevenis, Wolfang Frings, Dominik Gottwald, Felime Guimaraes, M. Holicki, Volker Marx, Ya N Muller, Carsten Clauss, H. Falter, Xu Huang, Jennifer Lopez Barillao, Thomas Moschny, Simon Pickartz, F. J. Alfaro, J. Escudero-Sahuquillo, P. García, F. Quiles, J. L. Sánchez, Adrián Castelló, José Duro, M. E. Gómez, E. S. Quintana‐O","doi":"10.1109/DSD57027.2022.00100","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00100","url":null,"abstract":"In order to enable Exascale computing, next generation interconnection networks must scale to hundreds of thousands of nodes, and must provide features to also allow the HPC, HPDA, and AI applications to reach Exascale, while benefiting from new hardware and software trends. RED-SEA will pave the way to the next generation of European Exascale interconnects, including the next generation of BXI, as follows: (i) specify the new architecture using hardware-software co-design and a set of applications representative of the new terrain of converging HPC, HPDA, and AI; (ii) test, evaluate, and/or implement the new architectural features at multiple levels, according to the nature of each of them, ranging from mathematical analysis and modeling, to simulation, or to emulation or implementation on FPGA testbeds; (iii) enable seamless communication within and between resource clusters, and therefore development of a high-performance low latency gateway, bridging seamlessly with Ethernet; (iv) add efficient network resource management, thus improving congestion resiliency, virtualization, adaptive routing, collective operations; (v) open the interconnect to new kinds of applications and hardware, with enhancements for end-to-end network services - from programming models to reliability, security, low- latency, and new processors; (vi) leverage open standards and compatible APIs to develop innovative reusable libraries and Fabrics management solutions.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123079713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Implementation of the Rainbow signature scheme on SoC FPGA","authors":"Tomás Preucil, Petr Socha, M. Novotný","doi":"10.1109/DSD57027.2022.00074","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00074","url":null,"abstract":"Thanks to the research progress, quantum computers are slowly becoming a reality and some companies already have their working prototypes. While this is great news for some, it also means that some of the encryption algorithms used today will be rendered unsafe and obsolete. Due to this fact, NIST (US National Institute of Standards and Technology) has been running a standardization process for quantum-resistant key exchange algorithms and digital signatures. One of these is Rainbow—a signature scheme based on the fact that solving a set of random multivariate quadratic system is an NP-hard problem. This work aims to develop an AXI-connected accelerator for the Rainbow signature scheme, specifically the Ia variant. The accelerator is highly parameterizable, allowing to choose the data bus width, directly affecting the FPGA area used. It is also possible to swap components to use the design for other variants of Rainbow. This allows for a comprehensive experimental evaluation of our design. The developed accelerator provides significant speedup compared to CPU-based computation. This paper includes detailed documentation of the design as well as performance and resource utilisation evaluation.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132625414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Monitoring Framework to Support Mixed-Criticality Applications on Multicore Platforms","authors":"Gautam Gala, Carlos Rodriguez, Gabriele Monaco, Javier Castillo, G. Fohler, Veaceslav Falico, S. Tverdyshev","doi":"10.1109/DSD57027.2022.00092","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00092","url":null,"abstract":"The automotive industry is looking into integrated architecture to combine multiple application subsystems of different criticalities on the readily available low-cost multicore platforms as they promise several benefits. However, it is difficult to achieve the required isolation and guarantees in such an architecture due to contention in shared resources, e.g., CPU, shared-bus, and memory (controller). This can cause unpredictable delays leading to deadline misses in real-time applications. We propose a low overhead modular monitoring framework to provide support for ensuring that the real-time applications meet their deadline when considering shared resource accesses, and helping to improve resource utilization so that best-effort applications can achieve a better Quality-of-Service despite pessimistic resource allocation assumptions of real-time applications. Our framework keeps the monitoring overheads to a minimum and triggered reaction meaningful by operating on the basis of low-level hardware and software signals, strategically checking resources, and triggering actions based on abstract availability of resources. We propose a Domain-Specific Language (DSL) to relieve the system designers from the tedious and error-prone job of configuring platform-specific parameters for the framework. Finally, this paper evaluates our monitoring framework based on an instantiation on a Xilinx Zynq UltraSacle multicore SoC running Linux and a simple industry-inspired use case.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133457236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigating Novel 3D Modular Schemes for Large Array Topologies: Power Modeling and Prototype Feasibility","authors":"Pakon Thuphairo, C. Bailey, Anthony Moulds, Jim Austin","doi":"10.1109/DSD57027.2022.00044","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00044","url":null,"abstract":"This paper presents the Tiled Computing Array (TCA), a simple, uniform, 3D-mesh packaging at inter-board level, for massively parallel computers. In particular, the power modelling and practical feasibility of the system is examined. TCA eliminates the need for hierarchical rackmount-structures and introduces short and immediate data channels in multiple physical orientations, allowing a more direct physical mapping of 3D computational topology to real hardware. A dedicated simulation platform has been developed, and an engineered prototype demonstrator has been built. This paper explores the feasibility of the TCA concept for current hardware technologies and systems, evaluates power modeling and validation, and highlights some of the novel design challenges associated with such a system. Evaluations of physical scalability toward large-scale systems are reported, showing that TCA is a promising approach.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116357241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"SNAP: Selective NTV Heterogeneous Architectures for Power-Efficient Edge Computing","authors":"R. Tonetto, A. C. S. Beck, G. Nazar","doi":"10.1109/DSD57027.2022.00055","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00055","url":null,"abstract":"While there is a growing need to process ML inference on the edge for improved latency and extra security, general-purpose solutions alone cannot cope with the increasing performance demand under power restrictions. Considering that systolic arrays are a prominent, but also power-hungry solution, we propose a methodology to enable their use in edge devices. For that, we propose SNAP, a selective Near-Threshold Voltage (NTV) strategy to explore heterogeneous MPSoCs with two voltage islands, one at NTV, and another at nominal voltage. By adopting a dynamic programming approach, SNAP may selectively apply NTV to the systolic array and to an optimal subset of cores in RISC- V-based MPSoCs, enabling ML acceleration on the edge. Combined with a smart application mapping, the strategy increases performance by up to 18.9 % over a nominal design within the same power limits.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114212237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"AxE: An Approximate-Exact Multi-Processor System-on-Chip Platform","authors":"A. S. Baroughi, Sini Huemer, H. Shahhoseini, N. Taherinejad","doi":"10.1109/DSD57027.2022.00018","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00018","url":null,"abstract":"Due to the ever-increasing complexity of computing tasks, emerging computing paradigms that increase efficiency, such as approximate computing, are gaining momentum. However, so far, the majority of proposed solutions for hardware-based approximation have been application-specific and/or limited to smaller units of the computing system and require engineering effort for integration into the rest of the system. In this paper, we present Approximate and Exact Multi-Processor system-on-chip (AxE) platform. AxE is the first general-purpose approximate Multi-Processor System-on-Chip (MPSoC). AxE is a heterogeneous RISC-V platform with exact and approximate cores that allows exploring hardware approximation for any application and using software instructions. Using the full capacity of an entire MPSoC, especially a heterogeneous one such as AxE, is an increasingly challenging problem. Therefore, we also propose a task mapping method for running exact and approximable applications on AxE. That is a mixed task mapping, in which applications are viewed as a set of tasks that can be run independently on different processors with different capabilities (exact or approximate). We evaluated our proposed method on AxE and reached a 32% average execution speed-up and 21% energy consumption saving with an average of 99.3% accuracy on three mixed workloads. We also ran a sample image processing application, namely gray-scale filter, on AxE and will present its results.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125178320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"moreMCU: A Runtime-reconfigurable RISC-V Platform for Sustainable Embedded Systems","authors":"Tobias Scheipel, Florian Angermair, M. Baunach","doi":"10.1109/DSD57027.2022.00013","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00013","url":null,"abstract":"As the number of embedded systems continues to grow, so does the amount of disposed electronic devices. This is mainly due to partially or fully outdated hardware, caused by new legal regulations in jurisdiction or cutting-edge features within a new generation of devices or hardware components. As most devices are designed without having long-term maintainability in mind and can be easily replaced without much monetary effort, it is often easier to dispose of them. This throw-away mentality, however, increases the carbon footprint enormously. Within this work, we propose a platform that can be used to design future embedded systems in a more sustainable way by preparing them for long-term hardware adaptations. To do so, we aim to make logic updatable and re-usable while the device stays operational. This is achieved by carefully co-designing an operating system and a microcontroller platform with reconfigurable logic. In this paper, we use a RISC-V-based microcontroller running on a field-programmable gate array. The said microcontroller is designed to feature a modular pipeline and replaceable on-chip peripherals alongside a partial reconfiguration controller that can hot-swap parts of the microcontroller while it is running. It is supported by an operating system that handles the reconfiguration as well as functionality emulation, in case it is not (yet) available in hardware. Both the hardware and the software are aware of each other and can manipulate shared data structures for the management of the reconfiguration concept. The experimental evaluation that was carried out on a Artix-7 device shows the proper operation alongside performance measurements and resource utilization of the on-the-fly reconfiguration of a proof-of-concept system without affecting the execution of the remainder of the system.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117076106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Decomposition of transition systems into sets of synchronizing Free-choice Petri Nets","authors":"Viktor Teren, J. Cortadella, T. Villa","doi":"10.1109/DSD57027.2022.00031","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00031","url":null,"abstract":"Petri nets and transition systems are two important formalisms used for modeling concurrent systems. One interesting problem in this domain is the creation of a Petri net with a reachability graph equivalent to a given transition system. This paper focuses on the creation of a set of synchronizing Free-choice Petri nets (FCPNs) from a transition system. FCPNs are more amenable for visualization and structural analysis while not being excessively simple, as in the case of state machines. The results show that with a small set of FCPNs, the complexity of the model can be reduced when compared to the synthesis of a monolithic Petri net.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127020684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}