2022 25th Euromicro Conference on Digital System Design (DSD)最新文献_第9页

An Approximate Carry Disregard Multiplier with Improved Mean Relative Error Distance and Probability of Correctness 具有改进的平均相对误差距离和正确概率的近似进位忽略乘法器

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00016

N. Amirafshar, A. S. Baroughi, H. Shahhoseini, N. Taherinejad

引用次数: 1

Evaluation of artificial neural networks for the detection of esophagus tumor cells in microscopic hyperspectral images 人工神经网络在显微高光谱图像中食道肿瘤细胞检测中的应用评价

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00116

Anna Schröder, M. Maktabi, R. Thieme, B. Jansen-Winkeln, I. Gockel, C. Chalopin

{"title":"Evaluation of artificial neural networks for the detection of esophagus tumor cells in microscopic hyperspectral images","authors":"Anna Schröder, M. Maktabi, R. Thieme, B. Jansen-Winkeln, I. Gockel, C. Chalopin","doi":"10.1109/DSD57027.2022.00116","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00116","url":null,"abstract":"Microscopic analysis of histological slides of cancer tissue samples is standardly performed under white light microscopy. Researchers demonstrated the potential of artificial intelligence (AI) methods for the automatic identification of tumor cells. Hyperspectral imaging (HSI) combined with AI approaches can improve the accuracy, reliability, and time of the analysis. In this work, a HSI camera was coupled with a standard microscope to acquire microscopic hyperspectral (HS) images of stained histological slides of esophagus cancer tissue of 95 patients. The HS images were analyzed with deep learning algorithms to discriminate healthy cells (squamous epithelium) and tumors (stroma tumor and esophagus adenocarcinoma EAC). Five models were considered: a 2D CNN, a 2D CNN preserving the spatial relationship between spectral layers, a 3D CNN, a pre-trained 3D CNN and a recurrent neural network (RNN). They were evaluated using a leave-one-patient-out cross-validation. The predicted two classes were visualized with false colors. The RNN obtained the highest quantitative results with an accuracy of 0.791, an AUC of 0.79 and a computing time of 7.57 s per 10,000 patches. The best visual result was obtained on two selected HS images with the 2D CNN model. The performance of the automatic classification was higher on tissue which has not been treated with previous neoadjuvant therapy. The combination of HSI with deep learning method is promising for the automatic analysis of histological slides for cancer diagnosis.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116645594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Towards Resilient QDI Pipeline Implementations 迈向弹性QDI管道实现

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00093

Zaheer Tabassam, A. Steininger

引用次数: 2

A YOLO v3-tiny FPGA Architecture using a Reconfigurable Hardware Accelerator for Real-time Region of Interest Detection 基于可重构硬件加速器的YOLO v3微型FPGA体系结构用于实时感兴趣区域检测

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00021

Viktor Herrmann, Justin Knapheide, Fritjof Steinert, B. Stabernack

{"title":"A YOLO v3-tiny FPGA Architecture using a Reconfigurable Hardware Accelerator for Real-time Region of Interest Detection","authors":"Viktor Herrmann, Justin Knapheide, Fritjof Steinert, B. Stabernack","doi":"10.1109/DSD57027.2022.00021","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00021","url":null,"abstract":"With the recent advances in the fields of machine learning, neural networks and deep-learning algorithms have become a prevalent subject of computer vision. Especially for tasks like object classification and detection Convolutional Neu-ronal Networks (CNNs) have surpassed the previous traditional approaches. In addition to these applications, CNNs can recently also be found in other applications. For example the parametrization of video encoding algorithms as used in our example is quite a new application domain. Especially CNN's high recognition rate makes them particularly suitable for finding Regions of Interest (ROIs) in video sequences, which can be used for adapting the data rate of the compressed video stream accordingly. On the downside, these CNN require an immense amount of processing power and memory bandwidth. Object detection networks such as You Only Look Once (YOLO) try to balance processing speed and accuracy but still rely on power-hungry GPUs to meet real-time requirements. Specialized hardware like Field Programmable Gate Array (FPGA) implementations proved to strongly reduce this problem while still providing sufficient computational power. In this paper we propose a flexible architecture for object detection hardware acceleration based on the YOLO v3-tiny model. The reconfigurable accelerator comprises a high throughput convolution engine, custom blocks for all additional CNN operations and a programmable control unit to manage on-chip execution. The model can be deployed without significant changes based on 32-bit floating point values and without further methods that would reduce the model accuracy. Experimental results show a high capability of the design to accelerate the object detection task with a processing time of 27.5 ms per frame. It is thus real-time-capable for 30 FPS applications at frequency of 200 MHz.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114578570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Hardware-Software Codesign of a CNN Accelerator CNN加速器的软硬件协同设计

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00054

Changjae Yi, Donghyun Kang, S. Ha

引用次数: 0

Coherency Traffic Reduction in Manycore Systems 多核系统的一致性流量减少

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00043

Erdem Derebaşoğlu, I. Kadayif, O. Ozturk

{"title":"Coherency Traffic Reduction in Manycore Systems","authors":"Erdem Derebaşoğlu, I. Kadayif, O. Ozturk","doi":"10.1109/DSD57027.2022.00043","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00043","url":null,"abstract":"With the increasing number of cores in manycore accelerators and chip multiprocessors (CMPs), it gets more challenging to provide cache coherency efficiently. Although the snooping-based protocols are appropriate solutions to small-scale systems, they are inefficient for large systems because of the limited bandwidth. Therefore, large-scale manycores require directory-based solutions where a hardware structure called directory holds the information. This directory keeps track of all memory blocks and which cache stores a copy of these blocks. The directory sends messages only to caches that store relevant blocks and also coordinate simultaneous accesses to a cache block. As directory-based protocols scale to many cores, performance, network-on-chip (NoC) traffic, and bandwidth become major problems. In this paper, we present software mechanisms to improve the effectiveness of directory-based cache coherency in manycore and multicore systems with shared memory. In multithreaded applications, some of the data accesses do not disrupt cache coherency, but they still produce coherency messages among cores such as read-only (private) data. However, if data is accessed by at least two cores and at least one of them is a write operation, it is called shared data and requires cache coherency. In our proposed system, private data and shared data are determined at compile time, and cache coherency protocol only applies to shared data. We implement our approach in two stages. First, we use Andersen's static pointer analysis to analyze the program and mark its private instructions, i.e., instructions that load or store private data. Then, we use these analyses to decide if cache coherency protocol will be applied or not at runtime. Our simulation results on parallel benchmarks show that our approach reduces cycle count, dynamic random access memory (DRAM) accesses, and coherency traffic up to 13%.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131944345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

MVSTT: A Multi-Value Computation-in-Memory based on Spin-Transfer Torque Memories MVSTT:一种基于自旋传递转矩存储器的多值内存计算

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00052

A. Jafari, M. Mayahinia, Soyed Tuhin Ahmed, Christopher Münch, M. Tahoori

{"title":"MVSTT: A Multi-Value Computation-in-Memory based on Spin-Transfer Torque Memories","authors":"A. Jafari, M. Mayahinia, Soyed Tuhin Ahmed, Christopher Münch, M. Tahoori","doi":"10.1109/DSD57027.2022.00052","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00052","url":null,"abstract":"Analog Computation-in-Memory (CiM) with emerging non-volatile memories leads to significant performance and energy efficiency. Spin-Transfer Torque Magnetic Memory (STT-MRAM) is one of the promising technologies for CiM architectures. Although STT-MRAM has various benefits, it does not have the potential to be used directly in analog multi-value CiM operations due to its limited levels of cell resistance states. In this paper, we propose a novel flexible multi-value design for STT-MRAM (MVSTT) with the potential to be used for multi-value CiM. In the multi-value CiM, we are able to have various 2s resistive state combinations from $s$ selected MTJs, which is not possible in the normal STT-MRAM CiM. The size of the MVSTT can be adjusted at run-time depending on the application's requirements. The benefits of the proposed scheme are quantified in representative applications such as multi-value matrix multiplications, which is the basic computation of Neural Networks applications. For the multi-value matrix multiplication, the energy, and delay gain is up to 9.7 × and 13.3 ×, respectively, to non-CiM matrix-vector-multiplication. Also, for the neural network, the proposed design allows up to a 32 × reduction in the STT-MRAM cells per crossbar to achieve a similar inference accuracy as the binarized neural network.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123698341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Abeto framework: a Solution for Heterogeneous IP Management Abeto框架:异构IP管理的解决方案

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00101

Antonio J. Sánchez, Y. Barrios, D. Ventura, Lucana Santos, R. Sarmiento

引用次数: 0

Analysis of Graph Processing in Reconfigurable Devices for Edge Computing Applications 边缘计算应用中可重构设备的图形处理分析

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00012

Kaan Olgu, Kris Nikov, J. Núñez-Yáñez

{"title":"Analysis of Graph Processing in Reconfigurable Devices for Edge Computing Applications","authors":"Kaan Olgu, Kris Nikov, J. Núñez-Yáñez","doi":"10.1109/DSD57027.2022.00012","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00012","url":null,"abstract":"Graph processing is an area that has received significant attention in recent years due to the substantial expansion in industries relying on data analytics. Alongside the vital role of finding relations in social networks, graph processing is also widely used in transportation to find optimal routes and biological networks to analyse sequences. The main bottleneck in graph processing is irregular memory accesses rather than computation intensity. Since computational intensity is not a driving factor, we propose a method to perform graph processing at the edge more efficiently. We believe current cloud computing solutions are still very costly and have latency issues. The results demonstrate the benefits of a dedicated sparse graph processing algorithm compared with dense graph processing when analysing data with low density. As graph datasets grow exponentially, traversal algorithms such as breadth-first search (BFS), fundamental to many graph processing applications and metrics, become more costly to compute. Our work focuses on reviewing other implementations of breadth-first search algorithms designed for low power systems and proposing our solution that utilises advanced enhancements to achieve a significant performance boost up to 9.2x better performance in terms of MTEPS compared to other state-of-the-art solutions with a power usage of 2.32W.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116456117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

SecDec: Secure Decode Stage thanks to masking of instructions with the generated signals SecDec:安全解码阶段，用生成的信号屏蔽指令

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00080

Gaëtan Leplus, O. Savry, L. Bossuet

引用次数: 0