2022 25th Euromicro Conference on Digital System Design (DSD)最新文献_第3页

A Resilient System Design to Boot a RISC-V MPSoC 启动RISC-V MPSoC的弹性系统设计

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00039

Antti Nurmi, Antti Rautakoura, Henri Lunnikivi, Timo D. Hämäläinen

{"title":"A Resilient System Design to Boot a RISC-V MPSoC","authors":"Antti Nurmi, Antti Rautakoura, Henri Lunnikivi, Timo D. Hämäläinen","doi":"10.1109/DSD57027.2022.00039","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00039","url":null,"abstract":"This paper presents a highly resilient boot process design for Ballast, a new RISC- V based multiprocessor system-on-chip (SoC). An open source RISC- V SoC was adapted as a bootstrap processor and customized to meet our requirement for guaranteed chip wake-up. We outline the characteristic challenges of implementing a large program into a read-only memory (ROM) used for booting and propose generally applica-ble workflows to verify the boot process for application specific integrated circuit (ASIC) synthesis. We implemented four distinct boot modes. Two modes that load a software bootloader autonomously from an SD card are implemented for a secure digital input output (SDIO) interface and for a serial peripheral interface (SPI), respectively. Another SDIO based mode allows for direct program execution from external memory, while the last mode is based on usage of a RISC- V debug module. The boot process was verified with instruction set simulation, register transfer level simulation, gate-level simulation and field-programmable gate array prototyping. We received the fabricated ASIC samples and were able to successfully boot the chip via all boot modes on our custom circuit board.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131282496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

CELR: Cloud Enhanced Local Reconstruction from low-dose sparse Scanning Electron Microscopy images 低剂量稀疏扫描电镜图像的云增强局部重建

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00083

F. Putter, Maurice Peemen, P. Potocek, R. Schoenmakers, H. Corporaal

{"title":"CELR: Cloud Enhanced Local Reconstruction from low-dose sparse Scanning Electron Microscopy images","authors":"F. Putter, Maurice Peemen, P. Potocek, R. Schoenmakers, H. Corporaal","doi":"10.1109/DSD57027.2022.00083","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00083","url":null,"abstract":"Current Scanning Electron Microscopy (SEM) acquisition techniques are far too slow to capture large volumes in a feasible time. One solution is to use low-dose and sparse imaging. By computationally denoising and inpainting an image with acceptable quality can be approximated. This approach, however, requires significant compute resources. Therefore, this paper proposes CELR, a framework, that hides the computationally expensive workload of reconstructing low-dose sparse SEM images, such that (delayed) live reconstruction is possible. Live reconstruction is possible by using Convolutional Neural Networks (CNNs) that approximate a classical reconstruction algorithm like GOAL. The reconstruction by CNNs is done locally, while recurring training of CNNs is done in the cloud. Moreover, training labels are generated by GOAL in the cloud. Next to the framework, this paper evaluates and optimizes the CNN reconstruction throughput by employing Nvidia's TensorRT. This paper also touches upon open research questions about on-the-fly CNN training. The combination of CELR and TensorRT enables large volume acquisitions with a dwell-time of $mathbf{1}mu s$ and 10% pixel coverage to be reconstructed on a single GPU.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133683215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hardware Support for Predictable Resource Sharing in Virtualized Heterogeneous Multicores 虚拟化异构多核中可预测资源共享的硬件支持

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00034

T. Sandmann, Jürgen Becker

引用次数: 0

Demystifying the TensorFlow Eager Execution of Deep Learning Inference on a CPU-GPU Tandem 揭秘TensorFlow在CPU-GPU串联上深度学习推理的急切执行

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00066

Paul Delestrac, L. Torres, D. Novo

{"title":"Demystifying the TensorFlow Eager Execution of Deep Learning Inference on a CPU-GPU Tandem","authors":"Paul Delestrac, L. Torres, D. Novo","doi":"10.1109/DSD57027.2022.00066","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00066","url":null,"abstract":"Machine Learning (ML) frameworks are tools that facilitate the development and deployment of ML models. These tools are major catalysts of the recent explosion in ML models and hardware accelerators thanks to their high programming abstraction. However, such an abstraction also obfuscates the run-time execution of the model and complicates the understanding and identification of performance bottlenecks. In this paper, we demystify how a modern ML framework manages code execution from a high-level programming language. We focus our work on the TensorFlow eager execution, which remains obscure to many users despite being the simplest mode of execution in TensorFlow. We describe in detail the process followed by the runtime to run code on a CPU-GPU tandem. We propose new metrics to analyze the framework's runtime performance overhead. We use our metrics to conduct in-depth analysis of the inference process of two Convolutional Neural Networks (CNNs) (LeNet-5 and ResNet-50) and a transformer (BERT) for different batch sizes. Our results show that GPU kernels execution need to be long enough to exploit thread parallelism, and effectively hide the runtime overhead of the ML framework.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131802598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hybrid Post-Quantum Enhanced TLS 1.3 on Embedded Devices 嵌入式设备上的混合后量子增强TLS 1.3

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00127

Dominik Marchsreiter, Martha Johanna Sepúlveda

引用次数: 3

Glioblastoma Classification in Hyperspectral Images by Nonlinear Unmixing 基于非线性解混的高光谱图像胶质母细胞瘤分类

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00118

Juan Nicolás Mendoza-Chavarría, Eric R. Zavala-Sánchez, Liliana Granados-Castro, I. A. Cruz-Guerrero, H. Fabelo, S. Ortega, Gustavo Marrero Callico, D. U. Campos‐Delgado

{"title":"Glioblastoma Classification in Hyperspectral Images by Nonlinear Unmixing","authors":"Juan Nicolás Mendoza-Chavarría, Eric R. Zavala-Sánchez, Liliana Granados-Castro, I. A. Cruz-Guerrero, H. Fabelo, S. Ortega, Gustavo Marrero Callico, D. U. Campos‐Delgado","doi":"10.1109/DSD57027.2022.00118","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00118","url":null,"abstract":"Glioblastoma is considered an aggressive tumor due to its rapid growth rate and diffuse pattern in various parts of the brain. Current in-vivo classification procedures are executed under the supervision of an expert. However, this methodology could be subjective and time-consuming. In this work, we propose a classification method for in-vivo hyperspectral brain images to identify areas affected by glioblastomas based on nonlinear spectral unmixing. This methodology follows a semi-supervised approach for the estimation of the end-members in a multi-linear model. To improve the classification results, we vary the number of end-members per-class to address spectral variability of each studied type of tissue. Once the set of end-members is obtained, the classification map is generated according to the end-member with the highest abundance in each pixel, followed by morphological operations to smooth the resulting maps. The classification results demonstrate that the proposed methodology generates high performance in the regions of interest, with an accuracy above 0.75 and 0.96 in the inter and intra-patient strategies, respectively. These results indicate that the proposed methodology has the potential to be used as an assistant tool in the diagnosis of glioblastoma in hyperspectral imaging.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"35 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116648087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

SMART: Investigating the Impact of Threshold Voltage Suppression in an In-SRAM Multiplication/Accumulation Accelerator for Accuracy Improvement in 65 nm CMOS Technology SMART:研究阈值电压抑制在sram内倍增/累积加速器中对65nm CMOS技术精度提高的影响

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00115

Saeed Seyedfaraji, B. Mesgari, Semeen Rehman

{"title":"SMART: Investigating the Impact of Threshold Voltage Suppression in an In-SRAM Multiplication/Accumulation Accelerator for Accuracy Improvement in 65 nm CMOS Technology","authors":"Saeed Seyedfaraji, B. Mesgari, Semeen Rehman","doi":"10.1109/DSD57027.2022.00115","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00115","url":null,"abstract":"State-of-the-art In-memory processing has recently emerged as the most promising solution to overcome design challenges related to data movement inside current computing systems. One of the approaches to performing In-memory processing is based on the analog behavior of the data stored inside the memory cell. Analog-based approaches proposed various system architectures for that. In this paper, we have investigated the effect of threshold voltage suppression on the access transistors of the In-SRAM multiplication and accumulation (MAC) accelerator to improve and enhance the performance of bit line (bit line bar) discharge rate that will increase the accuracy of MAC operation. We provide a comprehensive analytical analysis followed by circuit implementation, including a Monte-Carlo simulation by a 65nm CMOS technology. We confirmed the efficiency of our method (SMART) for a four-by-four-bit MAC operation. The proposed technique improves the accuracy while consuming 0.683 pJ per computation from a power supply of IV. Our novel technique presents less than 0.009 standard deviations for the worst-case incorrect output scenario.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115063697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A holistic hardware-software approach for fault-aware embedded systems 故障感知嵌入式系统的整体软硬件方法

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00099

F. Kempf, Christoph Kühbacher, C. Mellwig, S. Altmeyer, T. Ungerer, J. Becker

{"title":"A holistic hardware-software approach for fault-aware embedded systems","authors":"F. Kempf, Christoph Kühbacher, C. Mellwig, S. Altmeyer, T. Ungerer, J. Becker","doi":"10.1109/DSD57027.2022.00099","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00099","url":null,"abstract":"Fault detection and fault tolerance are a already crucial part of many embedded systems and will become even more important in the future. Reasons are the increasing complexity of software used in safety-critical environments and the trend to execute software components with varying criticality on the same hardware. We propose a novel approach for a flexible and adaptive fault handling. Our approach combines an adaptive hardware architecture with a flexible runtime environment to detect and handle faults. In this paper, we present the structure of a tile-based many-core architecture with runtime-adaptive lockstep cores and the design of a flexible dataflow software framework utilizing this hardware platform. We demonstrate that the hardware overhead for our adaptive lockstep concept and the hardware requirements of our runtime environment are minor and thus allow the use in embedded systems. Furthermore, we verified the fault detection and correction capabilities of both the hardware and software via a hardware fault injection mechanism. In addition, our runtime evaluation shows promising results for different redundancy concepts. For this purpose, we compare the execution time of software-only and hardware-only redundancy solutions as well as combinations of both with a non-redundant baseline for different benchmark applications.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115600016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Evaluation of Early-exit Strategies in Low-cost FPGA-based Binarized Neural Networks 基于低成本fpga的二值化神经网络早期退出策略评估

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00035

Minxuan Kong, Kris Nikov, J. Núñez-Yáñez

引用次数: 0

Adaptive Exploration Based Routing for Spatial Isolation in Mixed Criticality Systems 基于自适应探索的混合临界系统空间隔离路径

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00032

Nidhi Anantharajaiah, J. Becker

{"title":"Adaptive Exploration Based Routing for Spatial Isolation in Mixed Criticality Systems","authors":"Nidhi Anantharajaiah, J. Becker","doi":"10.1109/DSD57027.2022.00032","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00032","url":null,"abstract":"Applications of different criticality are increasingly sharing the same System-on-Chip platform to be cost and resource effective. On such mixed criticality systems, spatial partitioning of resources is a commonly utilized technique to prevent interference between applications. At the communication level, Network-on-Chip (NoC) used in such systems can aid by isolating network traffic within application regions. Topologies that can develop in such partitions can be regular or irregular requiring minimal and non-minimal routing. For the NoC to be flexible and support such varying network parameters, it is desirable that the routing algorithm can support communication for all possible topologies. Here, we investigate a topology agnostic routing algorithm based on Ant Colony Optimization (ACO) metaheuristic. The routing algorithm explores the NoC for feasible paths using special ant packets and discovers paths based on history of already utilized paths and local traffic information. We aim to decrease the exploration time overhead, by proposing an adaptive exploration technique. Compared to the static version, the proposed technique can decrease the exploration time overhead by upto 68% while maintaining comparable latency and throughput.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130658703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1