2022 25th Euromicro Conference on Digital System Design (DSD)最新文献_第4页

Program Committee: DSD 2022 项目委员会:DSD 2022

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/dsd57027.2022.00007

引用次数: 0

A Clustering-Based Scoring Mechanism for Malicious Model Detection in Federated Learning 联邦学习中基于聚类的恶意模型检测评分机制

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00038

Cem Caglayan, A. Yurdakul

引用次数: 0

Blind Data Adversarial Bit-flip Attack against Deep Neural Networks 针对深度神经网络的盲数据对抗性位翻转攻击

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00126

B. Ghavami, Mani Sadati, M. Shahidzadeh, Zhenman Fang, Lesley Shannon

引用次数: 2

Skeptical Dynamic Dependability Management for Automated Systems 自动化系统的怀疑动态可靠性管理

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00025

F. Arnez, Guillaume Ollier, A. Radermacher, Morayo Adedjouma, Simos Gerasimou, C. Mraidha, F. Terrier

{"title":"Skeptical Dynamic Dependability Management for Automated Systems","authors":"F. Arnez, Guillaume Ollier, A. Radermacher, Morayo Adedjouma, Simos Gerasimou, C. Mraidha, F. Terrier","doi":"10.1109/DSD57027.2022.00025","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00025","url":null,"abstract":"Dynamic Dependability Management (DDM) is a promising approach to guarantee and monitor the ability of safety-critical Automated Systems (ASs) to deliver the intended service with an acceptable risk level. However, the non-interpretability and lack of specifications of the Learning-Enabled Components (LECs) used in ASs make this mission particularly challenging. Some existing DDM techniques overcome these limitations by using probabilistic environmental perception knowledge associated with predicting behavior changes for the agents in the environment. We propose to improve these techniques with a supervisory system that considers hazard analysis and risk assessment from the design stage. This hazard analysis is based on a characterization of the AS's operational domain (i.e., its scenario space, including unsafe ones). The proposed supervisory system also considers the uncertainty estimation and interaction between AS components through the whole perception-planning-control pipeline. Our framework then proposes leveraging and handling uncertainty from LEC components toward building safer ASs.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126884536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

ESAS: Exponent Series based Approximate Square Root Design 基于指数级数的近似平方根设计

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00015

Omkar G. Ratnaparkhi, M. Rao

{"title":"ESAS: Exponent Series based Approximate Square Root Design","authors":"Omkar G. Ratnaparkhi, M. Rao","doi":"10.1109/DSD57027.2022.00015","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00015","url":null,"abstract":"Approximate computing is an emerging method-ology that offers hardware benefits when compared with the traditional computing design at the cost of accuracy. It is highly suitable for applications which does not require precision but rather try to preserve exactness of the outcome. Many arithmetic designs have evolved over the years using approximate methodologies. Square-root is one of the common yet complex hardware unit which is often employed in image processing and communication system design application. However not much hardware implementation of square-root function is seen. In this paper a novel square-root design is proposed that offers better accuracy, and improved hardware results compared to that of the previous works. The proposed design utilizes first two terms of exponent series expansion and applies two level of approximation to evolve not only hardware efficient square-root designs but also offer improved error characteristics. The approximate Square-root design was implemented in all the three data-formats including integer, fixed, and IEEE half precision floating point. The proposed designs were validated on Sobel Edge Detection algorithm and envelope detector for communication design to provide accelerated performance.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"0 0 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126337897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Prebypass: Software Register File Bypassing for Reduced Interconnection Architectures 预绕过:软件注册文件绕过减少互连架构

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00030

K. Vadivel, B. Bruin, Roel Jordans, H. Corporaal, P. Jääskeläinen

{"title":"Prebypass: Software Register File Bypassing for Reduced Interconnection Architectures","authors":"K. Vadivel, B. Bruin, Roel Jordans, H. Corporaal, P. Jääskeläinen","doi":"10.1109/DSD57027.2022.00030","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00030","url":null,"abstract":"Exposed Datapath Architectures (EDPAs) with aggressively pruned data-path connectivity, where not all function units in the design have connections to a centralized register file, are promising solutions for energy-efficient computation. A direct bypassing of data between function units without temporary copies to the register file is a prime optimization for programming such architectures. However, traditional compiler frameworks, such as LLVM, assume function-units connect to register-files and allocate all live variables in register-files. This leads to schedule inefficiencies in terms of instruction-level parallelism and reg-ister accesses in the EDPAs. To address these inefficiencies, we propose Prebypass; a new optimization pass for EDPA compiler backends. Experimental results on an EDPA class of architecture, Transport- Triggered Architecture, show that Prebypass improves the runtime, register reads, and register writes up to 16%, 26 %, and 37 % respectively, when the datapath is extremely pruned. Evaluation in a 28-nm FDSOI technology reveals that Prebypass improves the core-level Energy by 17.5 % over the current heuristic scheduler.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122201372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Development of a Hyperspectral Colposcope for Early Detection and Assessment of Cervical Dysplasia 用于宫颈发育不良早期检测和评估的高光谱阴道镜的研制

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00121

Carlos Vega, Raquel León, Norberto Medina, H. Fabelo, S. Ortega, F. Balea, Aday García, Margarita Medina, Silvia De León, Alicia Martín, G. Callicó

{"title":"Development of a Hyperspectral Colposcope for Early Detection and Assessment of Cervical Dysplasia","authors":"Carlos Vega, Raquel León, Norberto Medina, H. Fabelo, S. Ortega, F. Balea, Aday García, Margarita Medina, Silvia De León, Alicia Martín, G. Callicó","doi":"10.1109/DSD57027.2022.00121","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00121","url":null,"abstract":"The early detection of precancerous cervical lesions is essential to improve patient treatment and prognosis. Current methods of screening and diagnosis have improved the detection of these lesions but still present some critical limitations. Hyperspectral (HS) imaging is emerging as a new non-invasive and label-free imaging technique in the medical field for performing quick diagnosis of different diseases. This work describes the first step in the research and development process to present to the gynaecologist a new non-invasive tool to detect cervical neoplasia during routine medical procedures. This tool is based on a HS camera coupled to a colposcope, a primary tool already used in cervical examinations. The developed HS colposcope was validated by comparing the HS images obtained against the captures obtained with conventional optics. Results show the feasibility of the developed system to start a data acquisition campaign of cervical lesions targeting future developments of algorithms based on artificial intelligence.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126770594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

GPU Based Implementation for the Pre-Processing of Radar-Based Human Activity Recognition 基于GPU的雷达人体活动识别预处理实现

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00085

Alexandre Bordat, Petr Dobiáš, J. Kernec, David Guyard, Olivier Romain

{"title":"GPU Based Implementation for the Pre-Processing of Radar-Based Human Activity Recognition","authors":"Alexandre Bordat, Petr Dobiáš, J. Kernec, David Guyard, Olivier Romain","doi":"10.1109/DSD57027.2022.00085","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00085","url":null,"abstract":"The correlation between an ageing population glob- ally and the increased risk of falling is a real challenge for health care infrastructures. This calls for the development of new ways to monitor the elderly at home. The confidentiality of radar data coupled with its richness of information can address weaknesses of existing technologies, namely, privacy and acceptance. The radar data produce a large quantity of data that needs to be processed in real-time to ensure a timely detection of fall/critical events necessary for the well-being of the elderly. We introduce a new embedded architecture using a G PU allowing a gain in processing time compared to CPU alone. We used an off- the-shelf frequency-modulated continuous-wave (FMCW) radar (Ancortek model SDR 980AD2). It is followed by a pre-processing chain consisting of a Fast Fourier Transform, Filter and Short Time Fourier Transform (STFT) to obtain time-velocity maps or spectrograms to extract characteristics of human activities such as walking. An implementation with cuFFT on Jetson Xavier increases the performance margin for the downstream of the processing chain, the acceleration factor being 10.49 compared to state-of-the-art CPU architecture. Continuous monitoring of the subject will save lives, minimize injuries, reduce anxiety and prevent post-fall syndrome (PDS).","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"253 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121034040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Unlocking Sneak Path Analysis in Memristor Based Logic Design Styles 基于忆阻器的逻辑设计风格解锁潜行路径分析

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00111

K. Datta, S. Shirinzadeh, P. L. Thangkhiew, I. Sengupta, R. Drechsler

引用次数: 1

Sargantana: A 1 GHz+ In-Order RISC-V Processor with SIMD Vector Extensions in 22nm FD-SOI Sargantana:在22nm FD-SOI中具有SIMD矢量扩展的1 GHz+顺序RISC-V处理器

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00042

Víctor Soria Pardos, Max Doblas, Guillem López-Paradís, Gerard Candón, Narcís Rodas, Xavier Carril, Pau Fontova-Musté, Neiel Leyva, Santiago Marco-Sola, Miquel Moretó

{"title":"Sargantana: A 1 GHz+ In-Order RISC-V Processor with SIMD Vector Extensions in 22nm FD-SOI","authors":"Víctor Soria Pardos, Max Doblas, Guillem López-Paradís, Gerard Candón, Narcís Rodas, Xavier Carril, Pau Fontova-Musté, Neiel Leyva, Santiago Marco-Sola, Miquel Moretó","doi":"10.1109/DSD57027.2022.00042","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00042","url":null,"abstract":"The RISC-V open Instruction Set Architecture (ISA) has proven to be a solid alternative to licensed ISAs. In the past 5 years, a plethora of industrial and academic cores and accelerators have been developed implementing this open ISA. In this paper, we present Sargantana, a 64-bit processor based on RISC-V that implements the RV64G ISA, a subset of the vector instructions extension (RVV 0.7.1), and custom application-specific instructions. Sargantana features a highly optimized 7-stage pipeline implementing out-of-order write-back, register renaming, and a non-blocking memory pipeline. Moreover, Sar-gantana features a Single Instruction Multiple Data (SIMD) unit that accelerates domain-specific applications. Sargantana achieves a 1.26 GHz frequency in the typical corner, and up to 1.69 GHz in the fast corner using 22nm FD-SOI commercial technology. As a result, Sargantana delivers a 1.77× higher Instructions Per Cycle (IPC) than our previous 5-stage in-order DVINO core, reaching 2.44 CoreMark/MHz. Our core design delivers comparable or even higher performance than other state-of-the-art academic cores performance under Autobench EEMBC benchmark suite. This way, Sargantana lays the foundations for future RISC-V based core designs able to meet industrial-class performance requirements for scientific, real-time, and high-performance computing applications.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129113318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3