2022 25th Euromicro Conference on Digital System Design (DSD)最新文献_第2页

High-Level Synthesis of Geant4 Particle Transport Application for FPGA 高阶合成Geant4粒子输运在FPGA上的应用

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00020

Ramakant Joshi, Kuruvilla Varghese

{"title":"High-Level Synthesis of Geant4 Particle Transport Application for FPGA","authors":"Ramakant Joshi, Kuruvilla Varghese","doi":"10.1109/DSD57027.2022.00020","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00020","url":null,"abstract":"Geant4 is a software toolkit that simulates particle transport in matter and is widely used in high energy, nuclear, and medical physics applications. As target applications become more complex and time-critical, there is a need to explore custom hardware implementations of the code to reduce simulation times. Since the toolkit is written in $mathrm{C}++$, targeting a hand-coded RTL implementation is not feasible. In such scenarios, High-Level synthesis provides a promising alternative to synthesize untimed $mathbf{C}/mathbf{C}++$ code into optimized hardware. This paper presents the methodologies used to synthesize and optimize the Geant4 code for FPGA using High-Level synthesis, highlighting the challenges faced in the source-to-source transformation. We implement the Geant4 Tracking Algorithm taking Photon Transport in Water as the use case and comparing it with software implementation for functionality and performance. The scope of extending the methodology to complex use cases and its limitations are also discussed. The final implementation is based on the Xilinx Vitis tool flow targeted to the Xilinx Alveo U250 FPGA card.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133377743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Reviewers: DSD 2022 评审:DSD 2022

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/dsd57027.2022.00008

引用次数: 0

Evaluating Cryptographic Extensions On A RISC-V Simulation Environment 在RISC-V仿真环境下评估密码扩展

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00079

Parangat Sud, Shekoufeh Neisarian, E. Kavun

{"title":"Evaluating Cryptographic Extensions On A RISC-V Simulation Environment","authors":"Parangat Sud, Shekoufeh Neisarian, E. Kavun","doi":"10.1109/DSD57027.2022.00079","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00079","url":null,"abstract":"Due to the security requirement in the widely-deployed embedded applications, lightweight cryptographic ci-phers have been offered and used in resource-constrained devices in the last decades. In addition to the intrinsic low-cost properties of these ciphers, implementation-and architecture-specific techniques can make the implementation of these ciphers even more efficient. In this paper, we propose a simulation environment for the open-source RISC-V Instruction Set Architecture (ISA) implementing the base RISC-V ISA as well as the “bit manipulation” instruction set extension (ISE), which facilitates the imple-mentation of (lightweight) symmetric cryptography algorithms on resource-constrained devices efficiently. For demonstration pur-poses, we implement the lightweight block ciphers LEA, SIMON, and SPECK on our simulator and evaluate the performance of these ciphers on RISC-V architecture implemented with and without bit manipulation instructions. We define the performance of the lightweight ciphers as the total number of clock cycles required to encrypt one block of plaintext successfully. The performance of lightweight ciphers gives us an insight on how the performance of a cipher can be improved by using specific bit manipulation instructions. Our results show an average 38 % improvement in the total number of clock cycles required to run lightweight ciphers while using bit manipulation instructions.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127063684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

ARTS: An adaptive regularization training schedule for activation sparsity exploration 激活稀疏性探索的自适应正则化训练计划

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00062

Zeqi Zhu, Arash Pourtaherian, Luc Waeijen, Lennart Bamberg, E. Bondarev, Orlando Moreira

{"title":"ARTS: An adaptive regularization training schedule for activation sparsity exploration","authors":"Zeqi Zhu, Arash Pourtaherian, Luc Waeijen, Lennart Bamberg, E. Bondarev, Orlando Moreira","doi":"10.1109/DSD57027.2022.00062","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00062","url":null,"abstract":"Brain-inspired event-based processors have attracted considerable attention for edge deployment because of their ability to efficiently process Convolutional Neural Networks (CNNs) by exploiting sparsity. On such processors, one critical feature is that the speed and energy consumption of CNN inference are approximately proportional to the number of non-zero values in the activation maps. Thus, to achieve top performance, an efficient training algorithm is required to largely suppress the activations in CNNs. We propose a novel training method, called Adaptive-Regularization Training Schedule (ARTS), which dramatically decreases the non-zero activations in a model by adaptively altering the regularization coefficient through training. We evaluate our method across an extensive range of computer vision applications, including image classification, object recognition, depth estimation, and semantic segmentation. The results show that our technique can achieve 1.41 × to 6.00 × more activation suppression on top of ReLU activation across various networks and applications, and outperforms the state-of-the-art methods in terms of training time, activation suppression gains, and accuracy. A case study for a commercially-available event-based processor, Neuronflow, shows that the activation suppression achieved by ARTS effectively reduces CNN inference latency by up to 8.4 × and energy consumption by up to 14.1 ×.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128716477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Verification of Calculations of Non-Homogeneous Markov Chains Using Monte Carlo Simulation 用蒙特卡罗模拟验证非齐次马尔可夫链的计算

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00097

J. Reznícek, Martin Kohlík, H. Kubátová

引用次数: 0

Network on Privacy-Aware Audio-and Video-Based Applications for Active and Assisted Living: GoodBrother Project 积极生活和辅助生活的基于隐私意识的音频和视频应用网络:好兄弟项目

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00105

N. Sklavos, Maria Pantopoulou, Francisco Flórez-Revuelta

引用次数: 0

Suitability of ISAs for Data Paths Based on Redundant Number Systems: Is RISC-V the best? 基于冗余数字系统的isa数据路径的适用性:RISC-V是最好的吗?

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00041

Johannes Knödtel, Sebastian Rachuj, M. Reichenbach

{"title":"Suitability of ISAs for Data Paths Based on Redundant Number Systems: Is RISC-V the best?","authors":"Johannes Knödtel, Sebastian Rachuj, M. Reichenbach","doi":"10.1109/DSD57027.2022.00041","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00041","url":null,"abstract":"It has been known for a long time that in processor design, delay in arithmetic circuits can be reduced by using redundant number representations (RNS). This advantage is currently only exploited to a limited extent since various aspects complicate its use. For this reason the redundant representation is abandoned at the boundaries of the AL U and the values are reconverted back to the traditional binary representation. In particular, some operations that are traditionally considered fast are now subject to a higher delay. Among other concerns, this complicates comparison operations (e.g. equal to, greater than) and thus affects the timing behavior of conditional jumps. There is some initial research promising speedups using RNS in register files and the data path, but there are still some open questions. In particular it is important to evaluate how the instruction set is designed. Such a study is necessary to estimate whether it is worthwhile to develop the entire data path beyond the AL U in redundant representation. If no reconversion from redundant to traditional binary number system takes place, then e.g. the evaluation of condition codes or flags is problematic, since all speed advantages are lost again. In this work a qualitative and quantitative analysis of common ISAs in processors with redundant data paths is presented. All relevant properties of an ISA are identified and an evaluation of several common ISAs according to these criteria. A performance comparison of three common RISC ISAs (MIPS, A64 (ARM), RISC- V) is given based on a simulation of the Embench bench-mark suite using an adapted version of QEMU. This comparison estimates the speedup of processors with redundant versus binary data paths. It was found, that RISC- V was overall outperforming the other ISA with a maximum speedup of 1.41.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122358003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

SAT-based Exact Synthesis of Ternary Reversible Circuits using a Functionally Complete Gate Library 基于功能完备门库的三元可逆电路精确合成

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00108

Abhoy Kole, K. Datta, I. Sengupta, R. Drechsler

{"title":"SAT-based Exact Synthesis of Ternary Reversible Circuits using a Functionally Complete Gate Library","authors":"Abhoy Kole, K. Datta, I. Sengupta, R. Drechsler","doi":"10.1109/DSD57027.2022.00108","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00108","url":null,"abstract":"The problem of synthesis and optimization of reversible and quantum circuits have drawn the attention of researchers for the last two decades due to increasing interest in quantum computing. Although lot of works have been done on the synthesis of binary reversible circuits, very less works have been reported on the synthesis of ternary reversible circuits. Ternary circuits have lower cost of implementation as compared to their binary counterparts. However, the synthesis approaches that exist for ternary reversible circuits either use too many circuit lines (qutrits) or too many gates. Only one prior work has discussed the problem of generating cost-optimal ternary reversible circuits, but for a very restrictive gate library, which limits the approach to a specific subset of ternary reversible functions and often the solution becomes sub-optimal due to the imposed restrictions. The present paper overcomes that restriction, and uses multiple control ternary Toffoli gates with all possible ternary target operations as the gate library. This gate library is functionally complete and can be used to synthesize any arbitrary function. The proposed SAT-based synthesis approach provides low cost solutions in terms of the number of gates for any arbitrary ternary reversible function. Experimental results on various randomly generated permutations as well as standard ternary benchmarks establish this claim. The results can be used as template for other synthesis approaches by observing how far they deviate from the optimal solutions.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131697816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Combination of ROP Defense Mechanisms for Better Safety and Security in Embedded Systems 结合ROP防御机制提高嵌入式系统的安全性

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00070

Kai Lehniger, Mario Schölzel, Jonas Jelonek, P. Tabatt, Marcin Aftowicz, P. Langendörfer

引用次数: 3

A Supervisory Control Approach for Scheduling Real-time Periodic Tasks on Dynamically Reconfigurable Platforms 动态可重构平台上实时周期任务调度的监督控制方法

2022 25th Euromicro Conference on Digital System Design (DSD) Pub Date : 2022-08-01 DOI: 10.1109/DSD57027.2022.00010

Cherinet Kejela, R. Devaraj, A. Sarkar, S. Saha

{"title":"A Supervisory Control Approach for Scheduling Real-time Periodic Tasks on Dynamically Reconfigurable Platforms","authors":"Cherinet Kejela, R. Devaraj, A. Sarkar, S. Saha","doi":"10.1109/DSD57027.2022.00010","DOIUrl":"https://doi.org/10.1109/DSD57027.2022.00010","url":null,"abstract":"The dynamic partial reconfiguration (DPR) feature offered by modern FPGAs provides the flexibility of adapting the underlying hardware according to the needs of a particular situation at runtime, in response to application requirements. In recent times, DPR along with drastically reduced reconfiguration overheads has allowed the possibility of scheduling multiple real-time applications on FPGA platforms. However, in order to effectively harness the computation capacity of an FPGA floor, efficient techniques which can schedule real-time applications over both space and time are required. It may be noted that safety-critical systems often require resource-optimal solutions to reduce size, weight, cost and power consumption of the system. However, the scheduling of real-time tasks on FPGAs in the presence of non-negligible reconfigurationlcontext-switching overheads requires careful exploration of the state space which often makes it prohibitively expensive to be applied on-line. Hence, off-line formal approaches are often preferred in the design of reconfiguration controllers (i.e., schedulers) that are correct-by-construction as well as optimal in terms of usage of resources. In this paper, we propose a formal scheduler synthesis framework that generates an optimal scheduler for a set of non-preemptive periodic real-time tasks executing on a FPGA platform. We show the practical viability of our proposed framework by synthesizing schedulers for real-world benchmark applications and implementing them on FPGAs.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121083502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0