Suitability of ISAs for Data Paths Based on Redundant Number Systems: Is RISC-V the best?

Abstract

It has been known for a long time that in processor design, delay in arithmetic circuits can be reduced by using redundant number representations (RNS). This advantage is currently only exploited to a limited extent since various aspects complicate its use. For this reason the redundant representation is abandoned at the boundaries of the AL U and the values are reconverted back to the traditional binary representation. In particular, some operations that are traditionally considered fast are now subject to a higher delay. Among other concerns, this complicates comparison operations (e.g. equal to, greater than) and thus affects the timing behavior of conditional jumps. There is some initial research promising speedups using RNS in register files and the data path, but there are still some open questions. In particular it is important to evaluate how the instruction set is designed. Such a study is necessary to estimate whether it is worthwhile to develop the entire data path beyond the AL U in redundant representation. If no reconversion from redundant to traditional binary number system takes place, then e.g. the evaluation of condition codes or flags is problematic, since all speed advantages are lost again. In this work a qualitative and quantitative analysis of common ISAs in processors with redundant data paths is presented. All relevant properties of an ISA are identified and an evaluation of several common ISAs according to these criteria. A performance comparison of three common RISC ISAs (MIPS, A64 (ARM), RISC- V) is given based on a simulation of the Embench bench-mark suite using an adapted version of QEMU. This comparison estimates the speedup of processors with redundant versus binary data paths. It was found, that RISC- V was overall outperforming the other ISA with a maximum speedup of 1.41.