2016 IEEE International Test Conference (ITC)最新文献

Testing of interposer-based 2.5D integrated circuits 基于interposer的2.5D集成电路测试

2016 IEEE International Test Conference (ITC) Pub Date : 2017-03-21 DOI: 10.1109/TEST.2016.7805875

Ran Wang, K. Chakrabarty

引用次数: 3

A reconfigurable built-in memory self-repair architecture for heterogeneous cores with embedded BIST datapath 基于嵌入式BIST数据路径的异构核可重构内置内存自修复体系结构

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805870

V. Devanathan, Sumant Kale

{"title":"A reconfigurable built-in memory self-repair architecture for heterogeneous cores with embedded BIST datapath","authors":"V. Devanathan, Sumant Kale","doi":"10.1109/TEST.2016.7805870","DOIUrl":"https://doi.org/10.1109/TEST.2016.7805870","url":null,"abstract":"Stringent test-time and yield targets together with increased embedded memory content has resulted in increased power and area of memory self-test and repair logic. It is common for high performance IP cores (CPU/DSP/GPU/etc.) to have embedded BIST datapath (DP) that is shared with functional logic to minimize the IP BIST area overhead and ease IP design-closure. However, different IP cores (from same/different vendors) have diverse embedded BIST DP implementations. While having a dedicated memory self-test and repair controller for each IP simplifies design implementation, it is area and power intensive. In this paper, we propose a reconfigurable centralized memory built-in self-repair (BISR) architecture that supports multiple IPs with diverse embedded BIST DP implementations while being area efficient. We also present a power and timing-aware BISR synthesis flow that enables test time reduction while satisfying timing and power constraints. Experimental results on 28nm designs indicate about 2.4X area reduction compared to native EDA solution. The proposed solution also helps achieve 4.9X reduction in test time.","PeriodicalId":210661,"journal":{"name":"2016 IEEE International Test Conference (ITC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123149534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Efficient cross-layer concurrent error detection in nonlinear control systems using mapped predictive check states 基于映射预测检查状态的非线性控制系统的有效跨层并发错误检测

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805861

Suvadeep Banerjee, A. Chatterjee, J. Abraham

{"title":"Efficient cross-layer concurrent error detection in nonlinear control systems using mapped predictive check states","authors":"Suvadeep Banerjee, A. Chatterjee, J. Abraham","doi":"10.1109/TEST.2016.7805861","DOIUrl":"https://doi.org/10.1109/TEST.2016.7805861","url":null,"abstract":"The rapid proliferation of sensor networks and robots in a wide range of societal applications has focused renewed attention on error-free operation of their underlying signal processing and control functions for reasons of safety and reliability. While real-time error detection in linear systems has been investigated in the past, error detection in nonlinear control functions has largely relied on implementing redundancy in components, units, or subsystems resulting in excessive area/performance overheads. In this paper, we introduce a realtime error detection methodology for nonlinear control state space systems that uses mapped predictive check states for detecting sensor and actuator malfunctions and transient errors in the execution of the control algorithm on the underlying processor. In our approach, the check state at time t bears a known relationship with the corresponding states of the nonlinear system. This check state can also be predicted from knowledge of the prior system states and inputs using nonlinear mappings. Consistency between the prior known relationship and its predicted value above, is used to check for errors in system function. We demonstrate the proposed approach on two test cases - a classical nonlinear inverted pendulum balancing problem using a moving cart and a nonlinear sliding mode controller driven electromagnetic brake-by-wire (BBW) system. Simulation results show the effectiveness of the proposed approach for detecting degradation of the sensor and actuator functions and soft errors in the execution of the control algorithms.","PeriodicalId":210661,"journal":{"name":"2016 IEEE International Test Conference (ITC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117064759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Known-good-die test methods for large, thin, high-power digital devices 大、薄、高功率数字器件的已知好模测试方法

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805851

Dave Armstrong, G. Maier

引用次数: 3

Novel crosstalk evaluation method for high-density signal traces using clock waveform conversion technique 基于时钟波形转换技术的高密度信号走线串扰评估新方法

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805859

Takayuki Nakamura, Koji Asami

{"title":"Novel crosstalk evaluation method for high-density signal traces using clock waveform conversion technique","authors":"Takayuki Nakamura, Koji Asami","doi":"10.1109/TEST.2016.7805859","DOIUrl":"https://doi.org/10.1109/TEST.2016.7805859","url":null,"abstract":"Today, as LSI devices are increasingly more integrated resulting in larger number of package pins, high speed signal lines are more easily coupled to each other. Additionally, since multisite testing is required to reduce the cost of test, the transmission lines connecting these pins become even more concentrated. To measure these LSI devices, a huge number of high-speed transmission lines are required in the test board. Therefore minimizing crosstalk is very important. Furthermore, since the number of channels have reached more than ten thousand in recent evaluation systems, it is strongly required that the crosstalk from all channels be measured. With so many channels, measuring crosstalk with traditional methods will at best be very time-consuming or at worse, completely impractical, as it requires either a large number of pulse generators or physical reconnections depending on measurement type. In this paper, we propose a very fast and low cost crosstalk measurement method, which can acquire results very quickly and with high frequency resolution. Only a single measurement makes it possible to evaluate the crosstalk over a wide frequency band without the repetition of manually measuring at each frequency. This method is highly beneficial to the automatic test equipment (ATE) environment with high density transmission lines on the performance boards or load boards.","PeriodicalId":210661,"journal":{"name":"2016 IEEE International Test Conference (ITC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128798912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A unified test and fault-tolerant multicast solution for network-on-chip designs 片上网络设计的统一测试和容错组播解决方案

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805827

D. Xiang, K. Chakrabarty, H. Fujiwara

引用次数: 12

Logic characterization vehicle design reflection via layout rewiring 逻辑表征车辆设计反映通过布局重新布线

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805849

Phillip Fynan, Z. Liu, Ben Niewenhuis, Soumya Mittal, Marcin Strajwas, R. D. Blanton

{"title":"Logic characterization vehicle design reflection via layout rewiring","authors":"Phillip Fynan, Z. Liu, Ben Niewenhuis, Soumya Mittal, Marcin Strajwas, R. D. Blanton","doi":"10.1109/TEST.2016.7805849","DOIUrl":"https://doi.org/10.1109/TEST.2016.7805849","url":null,"abstract":"Continued scaling of semiconductor fabrication processes has made achieving yield targets increasingly difficult. The design and fabrication of various types of test vehicles is one approach for enabling fast yield learning. Recent work introduced the Carnegie Mellon logic characterization vehicle (CM-LCV). The CM-LCV design methodology uses regularity and existing testability theory to produce logic-based designs that are both highly testable and diagnosable. For the CM-LCV to be effective for yield learning, it must reflect the design characteristics of actual product layouts. Previous work enables incorporation of a standard-cell distribution derived from product designs into an LCV while simultaneously ensuring optimal testability. In this work, a new method is proposed for constructing a CM-LCV that reflects the design characteristics of a product through rewiring either the entire layout or some portion thereof. Four different approaches for rewiring are examined, and the results of each approach are evaluated using a variety of metrics. Experiment results reveal that a product layout can be easily rewired to construct an LCV with reasonable wirelength with reasonable CPU time. Rewiring has many advantages including the transformation of an actual product front-end to a logic-based test chip that has significant transparency to failure. Consequently, this means that front-end masks from an actual product can be re-used to create an effective LCV that is both more reflective and inexpensive to fabricate.","PeriodicalId":210661,"journal":{"name":"2016 IEEE International Test Conference (ITC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123665926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Advanced test methodology for complex SoCs 复杂soc的先进测试方法

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805857

Pavan Kumar Datla Jagannadha, Mahmut Yilmaz, Milind Sonawane, Sailendra Chadalavada, Shantanu Sarangi, Bonita Bhaskaran, Ayub Abdollahian

引用次数: 9

Power supply impedance emulation to eliminate overkills and underkills due to the impedance difference between ATE and customer board 电源阻抗仿真以消除由于ATE和客户板之间的阻抗差异而导致的过功耗和过功耗

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805860

T. Nakura, Naoki Terao, M. Ishida, R. Ikeno, Takashi Kusaka, T. Iizuka, K. Asada

{"title":"Power supply impedance emulation to eliminate overkills and underkills due to the impedance difference between ATE and customer board","authors":"T. Nakura, Naoki Terao, M. Ishida, R. Ikeno, Takashi Kusaka, T. Iizuka, K. Asada","doi":"10.1109/TEST.2016.7805860","DOIUrl":"https://doi.org/10.1109/TEST.2016.7805860","url":null,"abstract":"This paper proposes a new type of power supply circuit for automatic test equipment (ATE) that has ability to emulate arbitrary power supply impedance. It can emulate power supply impedance of customer environment so as to match the power supply voltage fluctuation waveforms of the ATE and of the customer environment, in order to eliminate overkills/underkills coming from the voltage fluctuation difference caused by the impedance difference between the ATE and a practical operating environment. Our technique adjusts the equivalent impedance by injecting compensation current by a current source attached in parallel with the power supply source. The compensation current is calculated and injected in realtime with a feedback manner based on the power supply voltage measurement with the impedance characteristics of ATE's original power delivery network (PDN) and the customer PDN. Experimental results of prototype circuits are demonstrated to show that the compensation current emulates the impedance, and the both power supply voltage fluctuation waveforms agree well. Limitations and applications of our method are also discussed.","PeriodicalId":210661,"journal":{"name":"2016 IEEE International Test Conference (ITC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122386715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Online slack-time binning for IO-registered die-to-die interconnects io注册模对模互连的在线空闲时间分组

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805848

Chih-Chieh Zheng, Shi-Yu Huang, Shyue-Kung Lu, Ting-Chi Wang, Kun-Han Tsai, Wu-Tung Cheng

{"title":"Online slack-time binning for IO-registered die-to-die interconnects","authors":"Chih-Chieh Zheng, Shi-Yu Huang, Shyue-Kung Lu, Ting-Chi Wang, Kun-Han Tsai, Wu-Tung Cheng","doi":"10.1109/TEST.2016.7805848","DOIUrl":"https://doi.org/10.1109/TEST.2016.7805848","url":null,"abstract":"In today's multi-die ICs, the die-to-die interconnects are often complicated and susceptible to various kinds of manufacturing defects and stress-induced performance degradation in the field. This phenomenon has prompted a need to perform online monitoring of the signal integrity over the die-to-die interconnects for reliability critical applications. In this work, we present a slack-time binning scheme so that one can constantly quantify the margin of a timing failure threat (TFT) occurring to a registered die-to-die interconnect. The proposed scheme attaches a Slack-Time Monitor (ST-monitor) to each Flip-Flop (FF) that receives a signal transmitted through a die-to-die interconnect under monitoring. Two techniques are introduced to enhance the traditional “Timing-Violation Checker”, namely (1) a tunable guard-band technique, and (2) an offset compensation technique. With these two techniques, one can perform online slack-time binning. Experimental results using a 90nm CMOS process show that the proposed scheme has a low area overhead of only approximately 2.35 times the area of a boundary scan cell.","PeriodicalId":210661,"journal":{"name":"2016 IEEE International Test Conference (ITC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129229580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0