Known-good-die test methods for large, thin, high-power digital devices

Abstract

The testing of large high-power devices which are destined for 2.5D or 3D applications requires many new techniques and solutions. This paper discusses some of the tradeoffs we looked at when striving to achieve true Known-Good-Devices (KGD) of large thin high-power logic devices. It is expected that the approach explored with this effort will significantly improve the post-assembly 2.5D/3D yield by bringing forward various high and low temperature tests which previously have not been possible to do. This paper discusses the challenges with wafer probing of this class of devices, analyzes the value of doing pre-insertion and/or partial assembly testing of this type of device. Also discussed in this paper are the various steps used to confirm the appropriateness of a recently introduced probe solution, Advantest HA1000, for meeting the demanding needs of singulated die level testing.